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feat: update project tt_um_MichaelBell_rle_vga from MichaelBell/tt07-…
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…rle-vga

Commit: 0bfa627d4491c6dadd1711ebced96b92c7f88681
Workflow: https://github.com/MichaelBell/tt07-rle-vga/actions/runs/9071294977
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed May 14, 2024
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Showing 9 changed files with 51,606 additions and 54,003 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_MichaelBell_rle_vga/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt07 dd5f1685",
"repo": "https://github.com/MichaelBell/tt07-rle-vga",
"commit": "75046359ea83d01b65bb62cfb96b7c53685b04b7",
"workflow_url": "https://github.com/MichaelBell/tt07-rle-vga/actions/runs/9053584052",
"commit": "0bfa627d4491c6dadd1711ebced96b92c7f88681",
"workflow_url": "https://github.com/MichaelBell/tt07-rle-vga/actions/runs/9071294977",
"sort_id": 1715542824814,
"openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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15 changes: 14 additions & 1 deletion projects/tt_um_MichaelBell_rle_vga/docs/info.md
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Expand Up @@ -12,15 +12,28 @@ You can also include images in this folder and reference them in the markdown. E
A 6bpp run length encoded image or video is read from a W25Q128JV or similar QSPI flash, and output to 640x480 VGA.

This is perfect for displaying the Bad Apple music video.

![A frame from Bad Apple, rendered by the FPGA version of this design](badapple.jpg)

### Run Length Encoding

The encoding uses 16-bit words. Most words are a run length in the top 10 bits, and a colour in the bottom 6 bits. A run must come to the end at the end of each row.

A row can be repeated by encoding a word `0xF800` + number of repeats at the end of a row.

A run must be at least 2 pixels, and any group of 3 consecutive runs within a row must be at least 24 pixels, otherwise the data buffer will empty. This could definitely be improved!

If input 3 is high, each frame is repeated once, so playback is 30Hz instead of 60Hz.

The data is read starting at address 0. The special word `0xFFC0` causes the player to stop and restart from address 0 at the beginning of the next frame, restarting the video. This could also be used to display a still image.

## How to test

Create a RLE binary file (docs/scripts to do this TBD) and load onto the flash. The pinout matches the [QSPI PMOD](https://github.com/mole99/qspi-pmod). Connect that to the bidi pins. Note the flash must support the h6B Fast Read Quad Output command, with 8 dummy cycles between address and data.

Connect the [Tiny VGA PMOD](https://github.com/mole99/tiny-vga) to the output pins.

Inputs 2-0 set the read latency for the SPI in half clock cycles, it's likely that will need to be set to 2 (set input 1 high and inputs 0 and 2 low). This latency depends on the total round trip time through the mux and out to the flash and back. Valid values are 0 to 4.
Inputs 2-0 set the read latency for the SPI in half clock cycles, it's likely that will need to be set to 2 (set input 1 high and inputs 0 and 2 low). This latency depends on the total round trip time through the mux and out to the flash and back. Valid values are 1 to 4.

Run with a 25MHz clock (or ideally 25.175MHz).

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2 changes: 1 addition & 1 deletion projects/tt_um_MichaelBell_rle_vga/info.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ pinout:
ui[0]: "SPI latency[0]"
ui[1]: "SPI latency[1]"
ui[2]: "SPI latency[2]"
ui[3]: ""
ui[3]: "30Hz select"
ui[4]: ""
ui[5]: ""
ui[6]: ""
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2 changes: 1 addition & 1 deletion projects/tt_um_MichaelBell_rle_vga/stats/metrics.csv
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_MichaelBell_rle_vga,wokwi,flow completed,0h2m45s0ms,0h2m19s0ms,154611.15517256744,0.01795472,77305.57758628372,78.36,82.2561,589.38,1192,0,0,0,0,0,0,0,0,0,0,-1,-1,33099,9703,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,17623930.0,0.0,68.46,46.5,22.46,3.67,-1,926,1409,95,529,0,0,0,1119,35,12,34,66,194,103,15,149,214,213,16,353,225,1,421,1388,2388,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,26.0,38.46153846153846,25,1,50,26.520,38.870,0.3,1,10,0.8,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_MichaelBell_rle_vga,wokwi,flow completed,0h2m21s0ms,0h1m54s0ms,152383.32872915867,0.01795472,76191.66436457934,77.73,80.7465,573.39,1182,0,0,0,0,0,0,0,0,0,0,-1,-1,29357,9279,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,16880183.0,0.0,62.25,44.29,17.14,3.12,-1,930,1409,96,526,0,0,0,1118,40,8,42,63,190,102,15,143,211,209,16,394,225,0,418,1368,2405,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,26.0,38.46153846153846,25,1,50,26.520,38.870,0.3,1,10,0.8,0,sky130_fd_sc_hd,AREA 0
105 changes: 56 additions & 49 deletions projects/tt_um_MichaelBell_rle_vga/stats/synthesis-stats.txt
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Expand Up @@ -3,67 +3,74 @@

=== tt_um_MichaelBell_rle_vga ===

Number of wires: 1176
Number of wire bits: 1211
Number of public wires: 223
Number of public wire bits: 258
Number of wires: 1166
Number of wire bits: 1201
Number of public wires: 219
Number of public wire bits: 254
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1192
sky130_fd_sc_hd__a211o_2 9
sky130_fd_sc_hd__a21bo_2 7
sky130_fd_sc_hd__a21o_2 52
sky130_fd_sc_hd__a21oi_2 34
sky130_fd_sc_hd__a221o_2 8
sky130_fd_sc_hd__a22o_2 29
sky130_fd_sc_hd__a2bb2o_2 6
Number of cells: 1182
sky130_fd_sc_hd__a2111o_2 1
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 14
sky130_fd_sc_hd__a21bo_2 9
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 27
sky130_fd_sc_hd__a21oi_2 31
sky130_fd_sc_hd__a221o_2 11
sky130_fd_sc_hd__a22o_2 21
sky130_fd_sc_hd__a22oi_2 1
sky130_fd_sc_hd__a2bb2o_2 7
sky130_fd_sc_hd__a311o_2 4
sky130_fd_sc_hd__a31o_2 18
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__a32o_2 6
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sky130_fd_sc_hd__and2b_2 2
sky130_fd_sc_hd__and3_2 35
sky130_fd_sc_hd__a31o_2 16
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32o_2 2
sky130_fd_sc_hd__a41o_2 1
sky130_fd_sc_hd__and2_2 48
sky130_fd_sc_hd__and2b_2 6
sky130_fd_sc_hd__and3_2 42
sky130_fd_sc_hd__and3b_2 8
sky130_fd_sc_hd__and4_2 10
sky130_fd_sc_hd__and4b_2 6
sky130_fd_sc_hd__and4_2 11
sky130_fd_sc_hd__and4b_2 7
sky130_fd_sc_hd__and4bb_2 1
sky130_fd_sc_hd__buf_1 141
sky130_fd_sc_hd__buf_1 146
sky130_fd_sc_hd__buf_2 9
sky130_fd_sc_hd__conb_1 8
sky130_fd_sc_hd__dfxtp_2 211
sky130_fd_sc_hd__inv_2 37
sky130_fd_sc_hd__mux2_2 113
sky130_fd_sc_hd__nand2_2 52
sky130_fd_sc_hd__dfxtp_2 207
sky130_fd_sc_hd__inv_2 34
sky130_fd_sc_hd__mux2_2 126
sky130_fd_sc_hd__nand2_2 55
sky130_fd_sc_hd__nand2b_2 1
sky130_fd_sc_hd__nand3_2 5
sky130_fd_sc_hd__nand3b_2 2
sky130_fd_sc_hd__nand4_2 3
sky130_fd_sc_hd__nor2_2 52
sky130_fd_sc_hd__nor2b_2 1
sky130_fd_sc_hd__nor3_2 4
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__o211a_2 38
sky130_fd_sc_hd__nand3_2 6
sky130_fd_sc_hd__nand4_2 6
sky130_fd_sc_hd__nand4b_2 1
sky130_fd_sc_hd__nor2_2 49
sky130_fd_sc_hd__nor3_2 2
sky130_fd_sc_hd__nor3b_2 2
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__o211a_2 31
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o21a_2 34
sky130_fd_sc_hd__o21ai_2 37
sky130_fd_sc_hd__o21ba_2 7
sky130_fd_sc_hd__o21bai_2 2
sky130_fd_sc_hd__o221a_2 1
sky130_fd_sc_hd__o22a_2 4
sky130_fd_sc_hd__o2bb2a_2 2
sky130_fd_sc_hd__o311a_2 1
sky130_fd_sc_hd__o21a_2 26
sky130_fd_sc_hd__o21ai_2 41
sky130_fd_sc_hd__o21ba_2 4
sky130_fd_sc_hd__o221a_2 3
sky130_fd_sc_hd__o22a_2 5
sky130_fd_sc_hd__o2bb2a_2 4
sky130_fd_sc_hd__o311a_2 2
sky130_fd_sc_hd__o31a_2 5
sky130_fd_sc_hd__o41a_2 2
sky130_fd_sc_hd__o41ai_2 1
sky130_fd_sc_hd__or2_2 48
sky130_fd_sc_hd__or3_2 17
sky130_fd_sc_hd__or3b_2 18
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 45
sky130_fd_sc_hd__or2b_2 3
sky130_fd_sc_hd__or3_2 15
sky130_fd_sc_hd__or3b_2 15
sky130_fd_sc_hd__or4_2 14
sky130_fd_sc_hd__or4b_2 7
sky130_fd_sc_hd__or4b_2 4
sky130_fd_sc_hd__or4bb_2 1
sky130_fd_sc_hd__xnor2_2 32
sky130_fd_sc_hd__xor2_2 4
sky130_fd_sc_hd__xor2_2 2

Chip area for module '\tt_um_MichaelBell_rle_vga': 12474.464000
Chip area for module '\tt_um_MichaelBell_rle_vga': 12374.368000

Binary file modified projects/tt_um_MichaelBell_rle_vga/tt_um_MichaelBell_rle_vga.gds
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Binary file not shown.
144 changes: 62 additions & 82 deletions projects/tt_um_MichaelBell_rle_vga/tt_um_MichaelBell_rle_vga.lef
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Expand Up @@ -67,7 +67,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN rst_n
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.159000 ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 151.190 110.520 151.490 111.520 ;
Expand All @@ -76,7 +76,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN ui_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 147.510 110.520 147.810 111.520 ;
Expand All @@ -85,7 +85,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN ui_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.159000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 143.830 110.520 144.130 111.520 ;
Expand All @@ -94,7 +94,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN ui_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 140.150 110.520 140.450 111.520 ;
Expand All @@ -103,6 +103,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN ui_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 136.470 110.520 136.770 111.520 ;
Expand Down Expand Up @@ -281,7 +282,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN uio_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 59.190 110.520 59.490 111.520 ;
Expand All @@ -290,7 +291,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN uio_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 55.510 110.520 55.810 111.520 ;
Expand Down Expand Up @@ -348,7 +349,7 @@ MACRO tt_um_MichaelBell_rle_vga
PIN uo_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 88.630 110.520 88.930 111.520 ;
Expand Down Expand Up @@ -411,93 +412,72 @@ MACRO tt_um_MichaelBell_rle_vga
PIN uo_out[7]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 62.870 110.520 63.170 111.520 ;
END
END uo_out[7]
OBS
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RECT 140.005 12.415 155.185 109.440 ;
END
END tt_um_MichaelBell_rle_vga
END LIBRARY
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