feat: update project tt_um_calonso88_74181 from calonso88/tt07_alu_74181

Commit: 59d3396f51e48622ddead116617eff98dfcd69d5 Workflow: https://github.com/calonso88/tt07_alu_74181/actions/runs/9323946760
TinyTapeout · May 31, 2024 · c5b9704 · c5b9704
1 parent 7fc73ea
commit c5b9704
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Showing 4 changed files with 7 additions and 7 deletions.
diff --git a/projects/tt_um_calonso88_74181/commit_id.json b/projects/tt_um_calonso88_74181/commit_id.json
@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt07 8e2da84a",
+  "app": "Tiny Tapeout tt07 11b2d371",
   "repo": "https://github.com/calonso88/tt07_alu_74181",
-  "commit": "89ecf0b7d8c0d7385cf92ac074a3499375c1ceb4",
-  "workflow_url": "https://github.com/calonso88/tt07_alu_74181/actions/runs/9197435230",
+  "commit": "59d3396f51e48622ddead116617eff98dfcd69d5",
+  "workflow_url": "https://github.com/calonso88/tt07_alu_74181/actions/runs/9323946760",
   "sort_id": 1716209094202,
   "openlane_version": "OpenLane2 2.0.7",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

diff --git a/projects/tt_um_calonso88_74181/docs/info.md b/projects/tt_um_calonso88_74181/docs/info.md
@@ -90,7 +90,7 @@ cmd = 0x00+addr, addr = 0 ~ 15
 
 ## How to test
 
-Use SPI1 Master peripheral in RP2040 to start communication on SPI interface towards this design. Remember to configure the SPI mode using the switches in DIP switch and configure the SPI mode in the RP2040 accordingly.
+Use SPI1 Master peripheral in RP2040 to start communication on SPI interface towards this design. Remember to configure the SPI mode using the switches in DIP switch (if you'd like to have CPOL=1 and CPHA=1). Alternatively, don't use the DIP switches and use the RP2040 GPIOs to configure the SPI mode in the desired mode.
 
 ## External hardware
 

diff --git a/projects/tt_um_calonso88_74181/stats/metrics.csv b/projects/tt_um_calonso88_74181/stats/metrics.csv
@@ -252,9 +252,9 @@ timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79919
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79984
 design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00080835
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000774048
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.000153636
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000774048
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000776905
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.000154849
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000776905
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
 ir__drop__avg,0.00016200000000000000749227069274382984076510183513164520263671875
 ir__drop__worst,0.000808000000000000015952517085082718040212057530879974365234375

diff --git a/projects/tt_um_calonso88_74181/tt_um_calonso88_74181.gds b/projects/tt_um_calonso88_74181/tt_um_calonso88_74181.gds