feat: update project tt_um_chess from Ravenslofty/tt07-chess

Commit: 345eb53a8432fd1dd7c0ba993eaaf76f79908fe0
Workflow: https://github.com/Ravenslofty/tt07-chess/actions/runs/9329625102

projects/tt_um_chess/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt07 8e2da84a",
+  "app": "Tiny Tapeout tt07 11b2d371",
   "repo": "https://github.com/Ravenslofty/tt07-chess",
-  "commit": "156b2bc8903d8aee7566fa0b7ca43650d23c4dab",
-  "workflow_url": "https://github.com/Ravenslofty/tt07-chess/actions/runs/9185357534",
+  "commit": "345eb53a8432fd1dd7c0ba993eaaf76f79908fe0",
+  "workflow_url": "https://github.com/Ravenslofty/tt07-chess/actions/runs/9329625102",
   "sort_id": 1716004510784,
   "openlane_version": "OpenLane2 2.0.7",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_chess/info.yaml

@@ -1,10 +1,10 @@
 # Tiny Tapeout project information
 project:
-  title:        "Belle"                # Project title
+  title:        "Chess"                # Project title
   author:       "Hannah Ravensloft"    # Your name
   discord:      "ravenslofty"          # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "chess move generator" # One line description of what your project does
-  language:     "Verilog"              # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "SystemVerilog"        # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0                      # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
@@ -14,8 +14,12 @@ project:
   top_module:  "tt_um_chess"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
-  source_files:        
-    - "project.v"
+  source_files:
+    - "arb.sv"
+    - "board.sv"
+    - "spi_rxtx.sv"
+    - "square.sv"
+    - "top.sv"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout: