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fix(tt_um_tnt_diff_rx): skip
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Causes DRC errors when hardening tt_top (due to a bug in the power strip generator that is triggered by a power strip < 1.42 us)
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urish committed Jun 1, 2024
1 parent a30c972 commit b3665bb
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Showing 90 changed files with 622,572 additions and 2 deletions.
9 changes: 9 additions & 0 deletions .vscode/settings.json
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{
"python.analysis.inlayHints.functionReturnTypes": true,
"python.analysis.inlayHints.variableTypes": true,
"python.analysis.typeCheckingMode": "strict",
"[python]": {
"editor.defaultFormatter": "ms-python.black-formatter"
},
"python.formatting.provider": "none"
}
4 changes: 4 additions & 0 deletions beol.sh
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#!/bin/sh

klayout -b -r ~/openmpw/mpw_precheck/checks/tech-files/sky130A_mr.drc -rd beol=true -rd input=projects/$1/$1.gds -rd topcell=$1 -rd report=drc_beol.xml
code projects/$1/drc_beol.xml
36 changes: 36 additions & 0 deletions default.cvcrc
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CVC_TOP = ''
CVC_NETLIST = ''
CVC_MODE = ''
CVC_MODEL_FILE = ''
CVC_POWER_FILE = ''
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = ''
CVC_REPORT_TITLE = ''
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
4 changes: 4 additions & 0 deletions feol.sh
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#!/bin/sh

klayout -b -r ~/openmpw/mpw_precheck/checks/tech-files/sky130A_mr.drc -rd feol=true -rd input=projects/$1/$1.gds -rd topcell=$1 -rd report=drc_feol.xml
code projects/$1/drc_feol.xml
4 changes: 4 additions & 0 deletions feol_re.sh
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#!/bin/sh
klayout -b -r ~/openmpw/mpw_precheck/checks/tech-files/sky130A_mr.drc -rd feol=true -rd input=reharden/$1/runs/wokwi/results/final/gds/$1.gds -rd topcell=$1 -rd report=drc_feol.xml
code reharden/$1/runs/wokwi/results/final/gds/drc_feol.xml
#klayout reharden/$1/runs/wokwi/results/final/gds/$1.gds
162 changes: 162 additions & 0 deletions fom_density.drc
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errs = 0
log("fom_density.drc:: sourcing design file=#{$gds_input} topcell=#{$top_cell} ...")
src = source($gds_input, $top_cell)
layout = src.layout
log("done.")


report("Density Checks", $report_file)

verbose(false)

diff_wildcard = "65/20"
tap_wildcard = "65/44"
fomfill_wildcard = "65,23/28"
fommk_wildcard = "23/0"

#$chip_boundary = input(235,4)
log("flattening chip boundary...")
$chip_boundary = input(235,4).flatten
log("done.")

$bbox = $chip_boundary.bbox

window_size = 700

if $step
step_size = $step.to_f
else
step_size = 70
end
log("step size = #{step_size}")

llx, lly, urx, ury = $bbox.left, $bbox.bottom, $bbox.right, $bbox.top
log("llx=#{llx} lly=#{lly} urx=#{urx} ury=#{ury}")
if urx-llx <= 0 || ury-lly <= 0
STDERR.puts "ERROR: fom_density.drc: fatal error, chip_boundary bbox empty or malformed"
errs += 1
end

cnt = 0
x_cnt = ((urx-step_size-llx) / step_size).ceil()
y_cnt = ((ury-step_size-lly) / step_size ).ceil()
tot = x_cnt * y_cnt
$fom_area_map = array = Array.new(x_cnt+1) { Array.new(y_cnt+1) { 0.0 } }
$tile_area_map = array = Array.new(x_cnt+1) { Array.new(y_cnt+1) { 0.0 } }

log("x_cnt = #{x_cnt}")
log("y_cnt = #{y_cnt}")

if x_cnt < 1 || y_cnt < 1
STDERR.puts "ERROR: fom_density.drc: fatal error, x-count or y-count < 1: #{x_cnt} #{y_cnt}"
errs += 1
end

# any errors till now?: abort.
if errs > 0
exit 1
end

class FomArea < RBA::TileOutputReceiver
def put(ix, iy, tile, obj, dbu, clip)
if tile
fom_area_scaled = obj.to_f * dbu * dbu
#tile_area_scaled = tile.area * dbu * dbu
tile_area_scaled = (tile & ($bbox * (1.0 / dbu))).area * dbu * dbu
#puts "got area for tile #{ix+1},#{iy+1}: #{fom_area_scaled.to_s} #{tile_area_scaled.to_s}"
$fom_area_map[ix][iy] += fom_area_scaled
$tile_area_map[ix][iy] = tile_area_scaled
else
puts "empty tile #{ix+1},#{iy+1}"
end
end
def finish(success)
puts "finish received: success = #{success}"
end

end

tp = RBA::TilingProcessor::new

# register the custom receiver
tp.output("my_receiver", FomArea::new)

tp.input("diff", layout.top_cell().begin_shapes_rec(layout.layer(65,20) ) )
tp.input("tap", layout.top_cell().begin_shapes_rec(layout.layer(65,44) ) )
tp.input("fomfill", layout.top_cell().begin_shapes_rec(layout.layer(23,28) ) )

tp.frame=$bbox
tp.tile_size(step_size, step_size) # 70x70 um tile size
log("dbu = #{layout.dbu}")
log("bbox_area = #{$bbox.area}")
tp.dbu = layout.dbu
tp.threads = $thr.to_i
# tp.scale_to_dbu = false

# The script clips the input at the tile and computes the (merged) area:
tp.queue("_output(my_receiver, _tile && ((diff | tap | fomfill) & _tile).area)")

log("calculating subtile areas (= #{tot})...")
tp.execute("Job description")

cnt = 0
big_x_cnt = ((urx-window_size-llx) / step_size).ceil()
big_y_cnt = ((ury-window_size-lly) / step_size).ceil()
big_tot = big_x_cnt * big_y_cnt
tiles_per_step = (window_size / step_size).ceil()
log("tiles per step = #{tiles_per_step}")
log("calculating window step densities (= #{big_tot})...")
markers_min = polygon_layer
markers_max = polygon_layer
min_err = 0
max_err = 0
min_density = 1
max_density = 0
for x in (0 ... big_x_cnt)
log("{{ CHECK }} #{cnt}/#{big_tot.round}")
for y in (0 ... big_y_cnt)
fom_area = 0
tile_area = 0
fom_density = 0
#$fom_area_map.slice(x, tiles_per_step).each { |a| a.slice(y, tiles_per_step).each { |b| puts "#{x},#{y} = #{b}" } }
$fom_area_map.slice(x, tiles_per_step).each { |a| a.slice(y, tiles_per_step).each { |b| fom_area+=b } }
$tile_area_map.slice(x, tiles_per_step).each { |a| a.slice(y, tiles_per_step).each { |b| tile_area+=b } }
marker_box = box(x * step_size, y* step_size, (x+tiles_per_step)*step_size, (y+tiles_per_step)*step_size)
if tile_area > 0
fom_density = fom_area / tile_area
#log("fom density #{cnt}/#{big_tot.round} is #{fom_density} for area #{tile_area}")
if fom_density < min_density
min_density = fom_density
end
if fom_density > max_density
max_density = fom_density
end
if fom_density < 0.33
min_err += 1
markers_min.insert(marker_box)
log("fom density below 0.33 : #{cnt}/#{big_tot.round} is #{"%.4f" % fom_density} for tile (#{marker_box.to_s}), area = #{tile_area.round}")
elsif fom_density > 0.57
max_err += 1
markers_max.insert(marker_box)
log("fom density above 0.57 : #{cnt}/#{big_tot.round} is #{"%.4f" % fom_density} for tile (#{marker_box.to_s}), area = #{tile_area.round}")
end
end
cnt += 1
end
end

log("minimum fom density = #{"%.4f" % min_density}")
log("maximum fom density = #{"%.4f" % max_density}")

if min_err > 0
log("cfom.pd.1d violations = #{min_err}")
markers_min.output("cfom.pd.1d", "0.33 min fom pattern density")
end

if max_err > 0
log("cfom.pd.1e violations = #{max_err}")
markers_max.output("cfom.pd.1e", "0.57 max fom pattern density")
end


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