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feat: update project tt_um_ccattuto_charmatrix from ccattuto/tt07-ser…
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…ial-charmatrix

Commit: b4a0c37648779f6fbfec74804602a6433f9b4ece
Workflow: https://github.com/ccattuto/tt07-serial-charmatrix/actions/runs/9069219957
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TinyTapeoutBot committed May 13, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_ccattuto_charmatrix/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt07 dd5f1685",
"repo": "https://github.com/ccattuto/tt07-serial-charmatrix",
"commit": "11b11d2dc7f74a9eead748675ea62df2f245772b",
"workflow_url": "https://github.com/ccattuto/tt07-serial-charmatrix/actions/runs/9065825511",
"commit": "b4a0c37648779f6fbfec74804602a6433f9b4ece",
"workflow_url": "https://github.com/ccattuto/tt07-serial-charmatrix/actions/runs/9069219957",
"sort_id": 1715616136626,
"openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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7 changes: 4 additions & 3 deletions projects/tt_um_ccattuto_charmatrix/docs/info.md
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Expand Up @@ -15,22 +15,23 @@ Up to 4 chained devices are supported for a maximum of 8 characters. The display

The project is designed to demonstrate the underlying Verilog modules, which should be easily re-usable:
- WS2812B LED strip driver
- UART receiver and transmitter
- UART receiver and transmitter (8N1 only, no flow control)
- linear-feedback pseudo-random number generator
- character ROM
The cocotb code to parse the [WS2812B protocol](https://cdn-shop.adafruit.com/datasheets/WS2812B.pdf) might also be useful to others.


## How to test

Basic setup:
* Connect `uo[0]` to the input pin (`DATA_IN`) of a [Pixie Chroma](https://connornishijima.github.io/Pixie_Chroma/) LED-matrix display (two 5x7 WS2812B LED matrices). Ensure the `VCC` and `GND` pins are connected to an adequate power source.
* Configure the inputt (e.g., using the DIP switches of the PCB) as follows: set `ui[0]` and `ui[1]` to `0` to use one Pixie Chrome (i.e., two 5x7 LED matrices); set `ui[2]` to `1` to enable UART echo; set `ui[4]` and `ui[5]` to disable LED dimming.
* Configure the input (e.g., using the DIP switches of the PCB) as follows: set `ui[0]` and `ui[1]` to `0` to use one Pixie Chrome (i.e., two 5x7 LED matrices); set `ui[2]` to `1` to enable UART echo; set `ui[4]` and `ui[5]` to `0` to disable LED dimming.
* Connect the UART interface of the project (RX is `ui[3]`, TX is `uo[4]`) to a serial terminal or a UART-to-USB PMOD or adapter (e.g., the one provided by the onboard RP2040 of the Tiny Tapeout PCB). Configure the serial interface for 9600 baud, 8 bits, 1 start bit, no parity bit, and 1 stop bit (8N1), with no hardware or software flow control.
* Open the terminal and type any characters: printable ASCII characters will appear from the right-hand side on the LED matrix and shift left as more characters are typed. Each character will appear with a different random color. Non-printable ASCII characters are shown as an empty rectangle. Received characters are echoed on the serial connection when `ui[2]` is set to `1`.

To use **more than one Pixie Chroma**, [chain](https://connornishijima.github.io/Pixie_Chroma/?section=datasheet) additional displays after the first one. This project supports up to 4 displays (e.g., 8 5x7 LED matrices). Set `ui[1]` and `ui[0]` (e.g., by using the DIP switches of the PCB) to configure the number of displays you are using: `00` for 1 display, `01` for 2 displays, `10` for 3 displays, and `11` for 4 displays (8 5x7 characters).

Dimming of the LED matrix is controlled by the `ui[5]` and `ui[4]` signals: `00` for no dimming, `01`, `10`, and `11` for decreasing luminosity.
Dimming of the LED matrix is controlled by the `ui[5]` and `ui[4]` signals: `00` for no dimming, `01`, `10`, and `11` for increasing dimming.

## External hardware

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2 changes: 1 addition & 1 deletion projects/tt_um_ccattuto_charmatrix/stats/metrics.csv
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@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_ccattuto_charmatrix,wokwi,flow completed,0h4m43s0ms,0h4m4s0ms,121549.40551390802,0.03634736,60774.70275695401,59.29,61.34119999999999,627.23,1976,0,0,0,0,0,0,0,0,0,0,-1,-1,78555,18000,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,48607104.0,0.0,62.37,69.32,12.61,33.49,-1,1789,2392,102,622,0,0,0,2062,83,20,82,35,323,69,30,576,302,292,17,1264,456,2,750,2209,4681,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_ccattuto_charmatrix,wokwi,flow completed,0h6m15s0ms,0h5m34s0ms,119843.64201416554,0.03634736,59921.82100708277,58.9,61.5092,620.66,1932,0,0,0,0,0,0,0,5,5,0,-1,-1,91083,18667,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,49076745.0,0.0,67.36,74.51,22.58,40.08,-1,1797,2400,102,622,0,0,0,2070,71,20,91,37,325,69,30,576,302,292,15,1197,456,21,736,2178,4588,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
118 changes: 57 additions & 61 deletions projects/tt_um_ccattuto_charmatrix/stats/synthesis-stats.txt
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Expand Up @@ -3,83 +3,79 @@

=== tt_um_ccattuto_charmatrix ===

Number of wires: 1960
Number of wire bits: 1995
Number of wires: 1916
Number of wire bits: 1951
Number of public wires: 304
Number of public wire bits: 339
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1976
sky130_fd_sc_hd__a2111o_2 6
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 24
Number of cells: 1932
sky130_fd_sc_hd__a2111o_2 4
sky130_fd_sc_hd__a211o_2 25
sky130_fd_sc_hd__a211oi_2 6
sky130_fd_sc_hd__a21bo_2 16
sky130_fd_sc_hd__a21boi_2 3
sky130_fd_sc_hd__a21bo_2 2
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 146
sky130_fd_sc_hd__a21oi_2 56
sky130_fd_sc_hd__a221o_2 16
sky130_fd_sc_hd__a221oi_2 2
sky130_fd_sc_hd__a22o_2 28
sky130_fd_sc_hd__a21oi_2 55
sky130_fd_sc_hd__a221o_2 20
sky130_fd_sc_hd__a22o_2 27
sky130_fd_sc_hd__a22oi_2 1
sky130_fd_sc_hd__a2bb2o_2 5
sky130_fd_sc_hd__a311o_2 9
sky130_fd_sc_hd__a311o_2 10
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 45
sky130_fd_sc_hd__a31o_2 58
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__a32o_2 24
sky130_fd_sc_hd__a41o_2 8
sky130_fd_sc_hd__and2_2 106
sky130_fd_sc_hd__and2b_2 8
sky130_fd_sc_hd__and3_2 174
sky130_fd_sc_hd__and3b_2 26
sky130_fd_sc_hd__and4_2 7
sky130_fd_sc_hd__and4b_2 6
sky130_fd_sc_hd__and4bb_2 1
sky130_fd_sc_hd__buf_1 227
sky130_fd_sc_hd__a32o_2 11
sky130_fd_sc_hd__a41o_2 4
sky130_fd_sc_hd__and2_2 74
sky130_fd_sc_hd__and2b_2 10
sky130_fd_sc_hd__and3_2 170
sky130_fd_sc_hd__and3b_2 30
sky130_fd_sc_hd__and4_2 11
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__buf_1 192
sky130_fd_sc_hd__buf_2 4
sky130_fd_sc_hd__conb_1 20
sky130_fd_sc_hd__dfxtp_2 295
sky130_fd_sc_hd__inv_2 44
sky130_fd_sc_hd__mux2_2 10
sky130_fd_sc_hd__mux4_2 8
sky130_fd_sc_hd__nand2_2 92
sky130_fd_sc_hd__nand2b_2 3
sky130_fd_sc_hd__inv_2 50
sky130_fd_sc_hd__mux2_2 23
sky130_fd_sc_hd__mux4_2 27
sky130_fd_sc_hd__nand2_2 99
sky130_fd_sc_hd__nand2b_2 5
sky130_fd_sc_hd__nand3_2 4
sky130_fd_sc_hd__nand3b_2 3
sky130_fd_sc_hd__nand4_2 2
sky130_fd_sc_hd__nor2_2 89
sky130_fd_sc_hd__nor2b_2 5
sky130_fd_sc_hd__nand3b_2 2
sky130_fd_sc_hd__nor2_2 121
sky130_fd_sc_hd__nor2b_2 3
sky130_fd_sc_hd__nor3_2 8
sky130_fd_sc_hd__nor3b_2 3
sky130_fd_sc_hd__nor4_2 2
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__o2111a_2 3
sky130_fd_sc_hd__o211a_2 46
sky130_fd_sc_hd__o211ai_2 5
sky130_fd_sc_hd__o21a_2 38
sky130_fd_sc_hd__o21ai_2 58
sky130_fd_sc_hd__o21ba_2 5
sky130_fd_sc_hd__o21bai_2 2
sky130_fd_sc_hd__o221a_2 54
sky130_fd_sc_hd__o221ai_2 2
sky130_fd_sc_hd__o22a_2 33
sky130_fd_sc_hd__o2bb2a_2 2
sky130_fd_sc_hd__o311a_2 8
sky130_fd_sc_hd__o311ai_2 1
sky130_fd_sc_hd__o31a_2 19
sky130_fd_sc_hd__o31ai_2 4
sky130_fd_sc_hd__o32a_2 19
sky130_fd_sc_hd__o41a_2 2
sky130_fd_sc_hd__or2_2 54
sky130_fd_sc_hd__or2b_2 10
sky130_fd_sc_hd__or3_2 20
sky130_fd_sc_hd__or3b_2 20
sky130_fd_sc_hd__or4_2 14
sky130_fd_sc_hd__or4b_2 4
sky130_fd_sc_hd__o2111ai_2 2
sky130_fd_sc_hd__o211a_2 50
sky130_fd_sc_hd__o211ai_2 6
sky130_fd_sc_hd__o21a_2 30
sky130_fd_sc_hd__o21ai_2 45
sky130_fd_sc_hd__o21ba_2 8
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 19
sky130_fd_sc_hd__o22a_2 23
sky130_fd_sc_hd__o22ai_2 1
sky130_fd_sc_hd__o2bb2a_2 16
sky130_fd_sc_hd__o311a_2 9
sky130_fd_sc_hd__o31a_2 13
sky130_fd_sc_hd__o31ai_2 3
sky130_fd_sc_hd__o32a_2 20
sky130_fd_sc_hd__o41a_2 4
sky130_fd_sc_hd__or2_2 59
sky130_fd_sc_hd__or2b_2 6
sky130_fd_sc_hd__or3_2 22
sky130_fd_sc_hd__or3b_2 19
sky130_fd_sc_hd__or4_2 21
sky130_fd_sc_hd__or4b_2 9
sky130_fd_sc_hd__or4bb_2 1
sky130_fd_sc_hd__xnor2_2 5
sky130_fd_sc_hd__xor2_2 2
sky130_fd_sc_hd__xnor2_2 8
sky130_fd_sc_hd__xor2_2 5

Chip area for module '\tt_um_ccattuto_charmatrix': 19610.057600
Chip area for module '\tt_um_ccattuto_charmatrix': 19483.686400

Binary file modified projects/tt_um_ccattuto_charmatrix/tt_um_ccattuto_charmatrix.gds
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119 changes: 60 additions & 59 deletions projects/tt_um_ccattuto_charmatrix/tt_um_ccattuto_charmatrix.lef
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Expand Up @@ -67,7 +67,7 @@ MACRO tt_um_ccattuto_charmatrix
PIN rst_n
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.247500 ;
ANTENNAGATEAREA 0.159000 ;
PORT
LAYER met4 ;
RECT 151.190 224.760 151.490 225.760 ;
Expand Down Expand Up @@ -112,7 +112,7 @@ MACRO tt_um_ccattuto_charmatrix
PIN ui_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.159000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 132.790 224.760 133.090 225.760 ;
Expand All @@ -121,7 +121,7 @@ MACRO tt_um_ccattuto_charmatrix
PIN ui_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.196500 ;
ANTENNAGATEAREA 0.159000 ;
PORT
LAYER met4 ;
RECT 129.110 224.760 129.410 225.760 ;
Expand Down Expand Up @@ -372,7 +372,7 @@ MACRO tt_um_ccattuto_charmatrix
PIN uo_out[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 73.910 224.760 74.210 225.760 ;
Expand All @@ -397,7 +397,7 @@ MACRO tt_um_ccattuto_charmatrix
PIN uo_out[7]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 62.870 224.760 63.170 225.760 ;
Expand All @@ -407,62 +407,63 @@ MACRO tt_um_ccattuto_charmatrix
LAYER li1 ;
RECT 2.760 2.635 158.240 223.125 ;
LAYER met1 ;
RECT 1.910 2.480 159.550 223.280 ;
RECT 0.530 0.380 159.040 225.720 ;
LAYER met2 ;
RECT 1.940 2.535 159.530 224.245 ;
RECT 0.550 0.350 159.010 225.750 ;
LAYER met3 ;
RECT 2.365 2.555 159.555 224.225 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.760 ;
RECT 8.370 224.360 10.950 224.760 ;
RECT 12.050 224.360 14.630 224.760 ;
RECT 15.730 224.360 18.310 224.760 ;
RECT 19.410 224.360 21.990 224.760 ;
RECT 23.090 224.360 25.670 224.760 ;
RECT 26.770 224.360 29.350 224.760 ;
RECT 30.450 224.360 33.030 224.760 ;
RECT 34.130 224.360 36.710 224.760 ;
RECT 37.810 224.360 40.390 224.760 ;
RECT 41.490 224.360 44.070 224.760 ;
RECT 45.170 224.360 47.750 224.760 ;
RECT 48.850 224.360 51.430 224.760 ;
RECT 52.530 224.360 55.110 224.760 ;
RECT 56.210 224.360 58.790 224.760 ;
RECT 59.890 224.360 62.470 224.760 ;
RECT 63.570 224.360 66.150 224.760 ;
RECT 67.250 224.360 69.830 224.760 ;
RECT 70.930 224.360 73.510 224.760 ;
RECT 74.610 224.360 77.190 224.760 ;
RECT 78.290 224.360 80.870 224.760 ;
RECT 81.970 224.360 84.550 224.760 ;
RECT 85.650 224.360 88.230 224.760 ;
RECT 89.330 224.360 91.910 224.760 ;
RECT 93.010 224.360 95.590 224.760 ;
RECT 96.690 224.360 99.270 224.760 ;
RECT 100.370 224.360 102.950 224.760 ;
RECT 104.050 224.360 106.630 224.760 ;
RECT 107.730 224.360 110.310 224.760 ;
RECT 111.410 224.360 113.990 224.760 ;
RECT 115.090 224.360 117.670 224.760 ;
RECT 118.770 224.360 121.350 224.760 ;
RECT 122.450 224.360 125.030 224.760 ;
RECT 126.130 224.360 128.710 224.760 ;
RECT 129.810 224.360 132.390 224.760 ;
RECT 133.490 224.360 136.070 224.760 ;
RECT 137.170 224.360 139.750 224.760 ;
RECT 140.850 224.360 143.430 224.760 ;
RECT 144.530 224.360 147.110 224.760 ;
RECT 148.210 224.360 150.790 224.760 ;
RECT 151.890 224.360 154.470 224.760 ;
RECT 3.975 223.680 155.185 224.360 ;
RECT 3.975 4.255 20.995 223.680 ;
RECT 23.395 4.255 40.430 223.680 ;
RECT 42.830 4.255 59.865 223.680 ;
RECT 62.265 4.255 79.300 223.680 ;
RECT 81.700 4.255 98.735 223.680 ;
RECT 101.135 4.255 118.170 223.680 ;
RECT 120.570 4.255 137.605 223.680 ;
RECT 140.005 4.255 155.185 223.680 ;
RECT 0.525 2.215 159.030 225.585 ;
LAYER met4 ;
RECT 3.055 224.360 3.590 225.585 ;
RECT 4.690 224.360 7.270 225.585 ;
RECT 8.370 224.360 10.950 225.585 ;
RECT 12.050 224.360 14.630 225.585 ;
RECT 15.730 224.360 18.310 225.585 ;
RECT 19.410 224.360 21.990 225.585 ;
RECT 23.090 224.360 25.670 225.585 ;
RECT 26.770 224.360 29.350 225.585 ;
RECT 30.450 224.360 33.030 225.585 ;
RECT 34.130 224.360 36.710 225.585 ;
RECT 37.810 224.360 40.390 225.585 ;
RECT 41.490 224.360 44.070 225.585 ;
RECT 45.170 224.360 47.750 225.585 ;
RECT 48.850 224.360 51.430 225.585 ;
RECT 52.530 224.360 55.110 225.585 ;
RECT 56.210 224.360 58.790 225.585 ;
RECT 59.890 224.360 62.470 225.585 ;
RECT 63.570 224.360 66.150 225.585 ;
RECT 67.250 224.360 69.830 225.585 ;
RECT 70.930 224.360 73.510 225.585 ;
RECT 74.610 224.360 77.190 225.585 ;
RECT 78.290 224.360 80.870 225.585 ;
RECT 81.970 224.360 84.550 225.585 ;
RECT 85.650 224.360 88.230 225.585 ;
RECT 89.330 224.360 91.910 225.585 ;
RECT 93.010 224.360 95.590 225.585 ;
RECT 96.690 224.360 99.270 225.585 ;
RECT 100.370 224.360 102.950 225.585 ;
RECT 104.050 224.360 106.630 225.585 ;
RECT 107.730 224.360 110.310 225.585 ;
RECT 111.410 224.360 113.990 225.585 ;
RECT 115.090 224.360 117.670 225.585 ;
RECT 118.770 224.360 121.350 225.585 ;
RECT 122.450 224.360 125.030 225.585 ;
RECT 126.130 224.360 128.710 225.585 ;
RECT 129.810 224.360 132.390 225.585 ;
RECT 133.490 224.360 136.070 225.585 ;
RECT 137.170 224.360 139.750 225.585 ;
RECT 140.850 224.360 143.430 225.585 ;
RECT 144.530 224.360 147.110 225.585 ;
RECT 148.210 224.360 150.790 225.585 ;
RECT 151.890 224.360 154.470 225.585 ;
RECT 3.055 223.680 155.185 224.360 ;
RECT 3.055 2.215 20.995 223.680 ;
RECT 23.395 2.215 40.430 223.680 ;
RECT 42.830 2.215 59.865 223.680 ;
RECT 62.265 2.215 79.300 223.680 ;
RECT 81.700 2.215 98.735 223.680 ;
RECT 101.135 2.215 118.170 223.680 ;
RECT 120.570 2.215 137.605 223.680 ;
RECT 140.005 2.215 155.185 223.680 ;
END
END tt_um_ccattuto_charmatrix
END LIBRARY
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