feat: update project tt_um_aidenfoxivey from aidenfoxivey/tt07-verilo…

…g-template

Commit: ad99cd0eea15a6364ec62136f5d11c1434b5e5a8
Workflow: https://github.com/aidenfoxivey/tt07-verilog-template/actions/runs/9011435901

projects/tt_um_aidenfoxivey/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt07 68e6da5b",
   "repo": "https://github.com/aidenfoxivey/tt07-verilog-template",
-  "commit": "76177e0973fa4df04ebf1816cce4e2b46c16f3d4",
-  "workflow_url": "https://github.com/aidenfoxivey/tt07-verilog-template/actions/runs/9006997059",
+  "commit": "ad99cd0eea15a6364ec62136f5d11c1434b5e5a8",
+  "workflow_url": "https://github.com/aidenfoxivey/tt07-verilog-template/actions/runs/9011435901",
   "sort_id": 1715194648872,
   "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_aidenfoxivey/docs/info.md

@@ -9,12 +9,16 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Hi
+`ui` should have the two bytes you want added to the CRC8. If you want to restart the internal CRC value, then pull `rst_n` low. That will set it back to the default 0x00. `enable` should be high unless you want to ignore the new calculated value from the specific clock cycle. You can add any number of two byte combinations to it and it will calculate the CRC8 CCITT value for the given combination.
+
+<https://crccalc.com> can help you calculate the CRC8 if you want.
+
+The specific polynomial in this case is 1+x^1+x^2+x^8.
 
 ## How to test
 
-Power on!
+Run `make` in the `/test` directory.
 
 ## External hardware
 
-None
+None required! The design is combinational, requiring only a small buffer to store the current CRC value. As a result, it's quite simple.

projects/tt_um_aidenfoxivey/info.yaml

@@ -3,7 +3,7 @@ project:
   title: "CRC-8 CCITT" # Project title
   author: "Aiden Fox Ivey" # Your name
   discord: "aidenfoxivey" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description: "A simple implementation of CRC-8 following CCITT specs." # One line description of what your project does
+  description: "A simple parallel implementation of CRC-8 following CCITT specs. This implies 0x00 is the start value." # One line description of what your project does
   language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)
 
@@ -20,27 +20,27 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "CRC input."
-  ui[1]: "CRC input."
-  ui[2]: "CRC input."
-  ui[3]: "CRC input."
-  ui[4]: "CRC input."
-  ui[5]: "CRC input."
-  ui[6]: "CRC input."
-  ui[7]: "CRC input."
+  ui[0]: "CRC input pin 0."
+  ui[1]: "CRC input pin 1."
+  ui[2]: "CRC input pin 2."
+  ui[3]: "CRC input pin 3."
+  ui[4]: "CRC input pin 4."
+  ui[5]: "CRC input pin 5."
+  ui[6]: "CRC input pin 6."
+  ui[7]: "CRC input pin 7."
 
   # Outputs
-  uo[0]: "CRC output."
-  uo[1]: "CRC output."
-  uo[2]: "CRC output."
-  uo[3]: "CRC output."
-  uo[4]: "CRC output."
-  uo[5]: "CRC output."
-  uo[6]: "CRC output."
-  uo[7]: "CRC output."
+  uo[0]: "CRC output pin 0."
+  uo[1]: "CRC output pin 1."
+  uo[2]: "CRC output pin 2."
+  uo[3]: "CRC output pin 3."
+  uo[4]: "CRC output pin 4."
+  uo[5]: "CRC output pin 5."
+  uo[6]: "CRC output pin 6."
+  uo[7]: "CRC output pin 7."
 
   # Bidirectional pins
-  uio[0]: ""
+  uio[0]: "Represents whether or not to ingest the values on ui to the CRC."
   uio[1]: ""
   uio[2]: ""
   uio[3]: ""

projects/tt_um_aidenfoxivey/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_aidenfoxivey,wokwi,flow completed,0h0m49s0ms,0h0m33s0ms,9245.479740146324,0.01795472,4622.739870073162,5.41,6.50888,489.12,70,0,0,0,0,0,0,0,0,0,0,-1,-1,1731,490,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1413628.0,0.0,4.01,1.64,1.31,0.63,-1,52,115,14,77,0,0,0,54,0,0,0,0,0,36,7,8,17,8,6,1196,225,0,253,83,1757,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_aidenfoxivey,wokwi,flow completed,0h0m49s0ms,0h0m34s0ms,9245.479740146324,0.01795472,4622.739870073162,5.41,6.50888,494.96,70,0,0,0,0,0,0,0,0,0,0,-1,-1,1731,490,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1413628.0,0.0,4.01,1.64,1.31,0.63,-1,52,115,14,77,0,0,0,54,0,0,0,0,0,36,7,8,17,8,6,1196,225,0,253,83,1757,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_aidenfoxivey/tt_um_aidenfoxivey.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_aidenfoxivey"
-*DATE "18:52:13 Wednesday May 08, 2024"
+*DATE "02:28:07 Thursday May 09, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "da0053d7b0014ab9c87ea148875ff6c2a0f9b658"