Skip to content

Commit

Permalink
feat: update project tt_um_emern_top from emern/badGPU
Browse files Browse the repository at this point in the history
Commit: b2012462b44ebcb668dfb620fde3fa3ace15170b
Workflow: https://github.com/emern/badGPU/actions/runs/9328429315
  • Loading branch information
TinyTapeoutBot authored and urish committed Jun 1, 2024
1 parent af351cd commit 68ff1de
Show file tree
Hide file tree
Showing 5 changed files with 15,785 additions and 15,806 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_emern_top/commit_id.json
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt07 11b2d371",
"repo": "https://github.com/emern/badGPU",
"commit": "912dc54d5279d3fb12d5430fadd6323395e07b1e",
"workflow_url": "https://github.com/emern/badGPU/actions/runs/9328021941",
"commit": "b2012462b44ebcb668dfb620fde3fa3ace15170b",
"workflow_url": "https://github.com/emern/badGPU/actions/runs/9328429315",
"sort_id": 1717224391974,
"openlane_version": "OpenLane2 2.0.7",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
240 changes: 123 additions & 117 deletions projects/tt_um_emern_top/stats/metrics.csv
Original file line number Diff line number Diff line change
Expand Up @@ -3,81 +3,81 @@ design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,25
design__inferred_latch__count,0
design__instance__count,15906
design__instance__area,107940
design__instance__count,15907
design__instance__area,107902
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,27
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,30
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.0008110080379992723
power__switching__total,0.00037431507371366024
power__leakage__total,1.066510790792563e-07
power__total,0.001185429748147726
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.140443
clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.140443
timing__hold__ws__corner:nom_tt_025C_1v80,0.333677
timing__setup__ws__corner:nom_tt_025C_1v80,10.821771
power__internal__total,0.0006333751371130347
power__switching__total,0.00030128355138003826
power__leakage__total,1.0679362105747714e-07
power__total,0.0009347654995508492
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.130924
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.130924
timing__hold__ws__corner:nom_tt_025C_1v80,0.345072
timing__setup__ws__corner:nom_tt_025C_1v80,15.797381
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.333677
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.345072
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,10.821771
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,15.797381
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,55
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,27
design__max_slew_violation__count__corner:nom_ss_100C_1v60,31
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,30
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.224299
clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.224299
timing__hold__ws__corner:nom_ss_100C_1v60,0.888616
timing__setup__ws__corner:nom_ss_100C_1v60,1.567624
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.200604
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.200604
timing__hold__ws__corner:nom_ss_100C_1v60,0.939033
timing__setup__ws__corner:nom_ss_100C_1v60,6.422692
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.888616
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.939033
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,1.567624
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,6.422692
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,27
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,30
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.105186
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.105186
timing__hold__ws__corner:nom_ff_n40C_1v95,0.115237
timing__setup__ws__corner:nom_ff_n40C_1v95,13.392184
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.099142
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.099142
timing__hold__ws__corner:nom_ff_n40C_1v95,0.120522
timing__setup__ws__corner:nom_ff_n40C_1v95,17.531597
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.115237
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.120522
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,14.126798
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,19.195637
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,65
design__max_fanout_violation__count,27
design__max_cap_violation__count,2
clock__skew__worst_hold,-0.100214
clock__skew__worst_setup,-0.236032
timing__hold__ws,0.113097
timing__setup__ws,1.342281
design__max_slew_violation__count,61
design__max_fanout_violation__count,30
design__max_cap_violation__count,0
clock__skew__worst_hold,0.217729
clock__skew__worst_setup,0.091599
timing__hold__ws,0.117748
timing__setup__ws,6.175952
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0.0
timing__setup__wns,0.0
timing__hold_vio__count,0
timing__hold_r2r__ws,0.113097
timing__hold_r2r__ws,0.117748
timing__hold_r2r_vio__count,0
timing__setup_vio__count,0
timing__setup_r2r__ws,1.342281
timing__setup_r2r__ws,6.175952
timing__setup_r2r_vio__count,0
design__die__bbox,0.0 0.0 682.64 225.76
design__core__bbox,2.76 2.72 679.88 223.04
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,154113
design__core__area,149183
design__instance__count__stdcell,15906
design__instance__area__stdcell,107940
design__instance__count__stdcell,15907
design__instance__area__stdcell,107902
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.723539
design__instance__utilization__stdcell,0.723539
design__instance__utilization,0.723287
design__instance__utilization__stdcell,0.723287
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count,0
Expand All @@ -100,166 +100,172 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,290830
route__wirelength__estimated,291149
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,75
antenna__violating__nets,14
antenna__violating__pins,24
route__antenna_violation__count,14
route__net,13767
antenna__violating__nets,11
antenna__violating__pins,31
route__antenna_violation__count,11
route__net,13768
route__net__special,2
route__drc_errors__iter:1,8732
route__wirelength__iter:1,324437
route__drc_errors__iter:2,4760
route__wirelength__iter:2,321607
route__drc_errors__iter:3,4249
route__wirelength__iter:3,320702
route__drc_errors__iter:4,722
route__wirelength__iter:4,320126
route__drc_errors__iter:5,129
route__wirelength__iter:5,320062
route__drc_errors__iter:6,0
route__wirelength__iter:6,320064
route__drc_errors__iter:1,9091
route__wirelength__iter:1,324546
route__drc_errors__iter:2,4947
route__wirelength__iter:2,321394
route__drc_errors__iter:3,5030
route__wirelength__iter:3,320632
route__drc_errors__iter:4,764
route__wirelength__iter:4,320054
route__drc_errors__iter:5,72
route__wirelength__iter:5,320027
route__drc_errors__iter:6,16
route__wirelength__iter:6,320035
route__drc_errors__iter:7,6
route__wirelength__iter:7,320045
route__drc_errors__iter:8,2
route__wirelength__iter:8,320060
route__drc_errors__iter:9,0
route__wirelength__iter:9,320060
route__drc_errors,0
route__wirelength,320064
route__vias,96377
route__vias__singlecut,96377
route__wirelength,320060
route__vias,96966
route__vias__singlecut,96966
route__vias__multicut,0
design__disconnected_pin__count,14
design__critical_disconnected_pin__count,0
route__wirelength__max,782.97
route__wirelength__max,862.53
timing__unannotated_net__count__corner:nom_tt_025C_1v80,29
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,29
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,29
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,27
design__max_fanout_violation__count__corner:min_tt_025C_1v80,30
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.133532
clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.133532
timing__hold__ws__corner:min_tt_025C_1v80,0.329819
timing__setup__ws__corner:min_tt_025C_1v80,11.002307
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.122056
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.122056
timing__hold__ws__corner:min_tt_025C_1v80,0.340956
timing__setup__ws__corner:min_tt_025C_1v80,15.968655
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0.0
timing__setup__wns__corner:min_tt_025C_1v80,0.0
timing__hold_vio__count__corner:min_tt_025C_1v80,0
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.329819
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.340956
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,11.002307
timing__setup_r2r__ws__corner:min_tt_025C_1v80,15.968655
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,29
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,16
design__max_fanout_violation__count__corner:min_ss_100C_1v60,27
design__max_slew_violation__count__corner:min_ss_100C_1v60,4
design__max_fanout_violation__count__corner:min_ss_100C_1v60,30
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.212701
clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.212701
timing__hold__ws__corner:min_ss_100C_1v60,0.880916
timing__setup__ws__corner:min_ss_100C_1v60,1.853366
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.187011
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.187011
timing__hold__ws__corner:min_ss_100C_1v60,0.934006
timing__setup__ws__corner:min_ss_100C_1v60,6.743273
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0.0
timing__setup__wns__corner:min_ss_100C_1v60,0.0
timing__hold_vio__count__corner:min_ss_100C_1v60,0
timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.880916
timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.934006
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,1.853366
timing__setup_r2r__ws__corner:min_ss_100C_1v60,6.743273
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,29
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,27
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,30
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.100214
clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.100214
timing__hold__ws__corner:min_ff_n40C_1v95,0.113097
timing__setup__ws__corner:min_ff_n40C_1v95,13.518018
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.091599
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.091599
timing__hold__ws__corner:min_ff_n40C_1v95,0.117748
timing__setup__ws__corner:min_ff_n40C_1v95,17.648336
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.113097
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.117748
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,14.286589
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,19.329052
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,29
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,27
design__max_cap_violation__count__corner:max_tt_025C_1v80,2
clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.148194
clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.148194
timing__hold__ws__corner:max_tt_025C_1v80,0.337581
timing__setup__ws__corner:max_tt_025C_1v80,10.649771
design__max_fanout_violation__count__corner:max_tt_025C_1v80,30
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.143787
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.143787
timing__hold__ws__corner:max_tt_025C_1v80,0.347543
timing__setup__ws__corner:max_tt_025C_1v80,15.670644
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0.0
timing__setup__wns__corner:max_tt_025C_1v80,0.0
timing__hold_vio__count__corner:max_tt_025C_1v80,0
timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.337581
timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.347543
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,10.649771
timing__setup_r2r__ws__corner:max_tt_025C_1v80,15.670644
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,29
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,65
design__max_fanout_violation__count__corner:max_ss_100C_1v60,27
design__max_cap_violation__count__corner:max_ss_100C_1v60,2
clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.236032
clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.236032
timing__hold__ws__corner:max_ss_100C_1v60,0.895988
timing__setup__ws__corner:max_ss_100C_1v60,1.342281
design__max_slew_violation__count__corner:max_ss_100C_1v60,61
design__max_fanout_violation__count__corner:max_ss_100C_1v60,30
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.217729
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.217729
timing__hold__ws__corner:max_ss_100C_1v60,0.942426
timing__setup__ws__corner:max_ss_100C_1v60,6.175952
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0.0
timing__setup__wns__corner:max_ss_100C_1v60,0.0
timing__hold_vio__count__corner:max_ss_100C_1v60,0
timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.895988
timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.942426
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,1.342281
timing__setup_r2r__ws__corner:max_ss_100C_1v60,6.175952
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,29
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,27
design__max_cap_violation__count__corner:max_ff_n40C_1v95,2
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.110231
clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.110231
timing__hold__ws__corner:max_ff_n40C_1v95,0.117114
timing__setup__ws__corner:max_ff_n40C_1v95,13.288505
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,30
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.110355
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.110355
timing__hold__ws__corner:max_ff_n40C_1v95,0.122428
timing__setup__ws__corner:max_ff_n40C_1v95,17.426033
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.117114
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122428
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,14.006678
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,19.083998
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,29
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,29
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79976
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79998
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000236724
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000207471
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000161684
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000207471
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79982
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00017732
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000192452
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000122719
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000192452
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.000016200000000000000749227069274382984076510183513164520263671875
ir__drop__worst,0.00023699999999999998736947837141286754558677785098552703857421875
ir__drop__avg,0.00001230000000000000081983031474663903281907550990581512451171875
ir__drop__worst,0.00017699999999999999262569050362259304165490902960300445556640625
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
Binary file modified projects/tt_um_emern_top/tt_um_emern_top.gds
Binary file not shown.
Loading

0 comments on commit 68ff1de

Please sign in to comment.