feat: update project tt_um_ccattuto_conway from ccattuto/tt07-conway-…

…term

Commit: d88b0fc03042fd7e3c21c2dca2136ca91c68beb0
Workflow: https://github.com/ccattuto/tt07-conway-term/actions/runs/9203888634

projects/tt_um_ccattuto_conway/LICENSE

@@ -0,0 +1,201 @@
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projects/tt_um_ccattuto_conway/commit_id.json

@@ -0,0 +1,9 @@
+{
+  "app": "Tiny Tapeout tt07 8e2da84a",
+  "repo": "https://github.com/ccattuto/tt07-conway-term",
+  "commit": "d88b0fc03042fd7e3c21c2dca2136ca91c68beb0",
+  "workflow_url": "https://github.com/ccattuto/tt07-conway-term/actions/runs/9203888634",
+  "sort_id": 1716450032055,
+  "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
+}

projects/tt_um_ccattuto_conway/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+
+## How it works
+
+This projects simulates [Conway's Game of Life](https://en.wikipedia.org/wiki/Conway%27s_Game_of_Life) in hardware on a small (32x16) grid with periodic boundary conditions. At each time step, the output of the simulation is printed to an ANSI serial terminal over a serial (UART) interface. The initial state of the board is pseudo-random, generated using a linear-feedback shift register. Single characters received over the serial interface are used to control the simulation, according to the following table:
+* `<space>`: start/stop simulation
+* `0`: randomize state
+* `1`: single-step the simulation
+
+The UART interface of the project is exposed according the the Tiny Tapeout recommended pinout, with `ui_in[3]` used for RX signal and `uo_out[4]` for TX. The UART is configured as 8N1 at 115200 baud, with no flow control.
+
+
+## How to test
+
+Connected the UART interface of the project to any UART terminal, or to an UART-to-USB PMOD or adapter, e.g., the one provided by the onboard RP2040 of the PCB. Configure the serial interface for 8 bits, 1 start bit, no parity bit, 1 stop bit (8N1), with no hardware or software flow control. Open the terminal and type any characters: this will bring up a welcome message explaining how to control the simulation.
+
+
+## External hardware
+
+UART terminal, or UART-to-USB adapter (PMOD or on-board via RP2040).
+

projects/tt_um_ccattuto_conway/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "Conway's Terminal"      # Project title
+  author:       "Ciro Cattuto"      # Your name
+  discord:      "ccattuto"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "A simulation of Conways' Game of Life visualized to an ANSI terminal over UART" # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     24000000       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_ccattuto_conway"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "project.v"
+    - "lfsr_rng.v"
+    - "UARTTransmitter.v"
+    - "UARTReceiver.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: ""
+  ui[1]: ""
+  ui[2]: ""
+  ui[3]: "UART RX"
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
+
+  # Outputs
+  uo[0]: ""
+  uo[1]: ""
+  uo[2]: ""
+  uo[3]: ""
+  uo[4]: "UART TX"
+  uo[5]: ""
+  uo[6]: ""
+  uo[7]: ""
+
+  # Bidirectional pins
+  uio[0]: ""
+  uio[1]: ""
+  uio[2]: ""
+  uio[3]: ""
+  uio[4]: ""
+  uio[5]: ""
+  uio[6]: ""
+  uio[7]: ""
+
+# Do not change!
+yaml_version: 6

projects/tt_um_ccattuto_conway/stats/metrics.csv

@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_ccattuto_conway,wokwi,flow completed,0h2m27s0ms,0h1m51s0ms,118853.19869173442,0.03634736,59426.59934586721,57.2,61.757600000000004,583.01,1858,0,0,0,0,0,0,0,0,0,0,-1,-1,43657,14034,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,27328546.0,0.0,37.96,45.38,0.92,6.96,-1,2005,2271,192,391,0,0,0,2159,73,30,95,46,475,60,33,337,328,326,16,1386,456,0,838,2160,4840,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_ccattuto_conway/stats/synthesis-stats.txt

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+
+66. Printing statistics.
+
+=== tt_um_ccattuto_conway ===
+
+   Number of wires:               1842
+   Number of wire bits:           1877
+   Number of public wires:         315
+   Number of public wire bits:     350
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:               1858
+     sky130_fd_sc_hd__a211o_2       20
+     sky130_fd_sc_hd__a211oi_2       1
+     sky130_fd_sc_hd__a21bo_2        2
+     sky130_fd_sc_hd__a21boi_2       4
+     sky130_fd_sc_hd__a21o_2        37
+     sky130_fd_sc_hd__a21oi_2       34
+     sky130_fd_sc_hd__a221o_2        9
+     sky130_fd_sc_hd__a22o_2        33
+     sky130_fd_sc_hd__a22oi_2        1
+     sky130_fd_sc_hd__a311o_2        4
+     sky130_fd_sc_hd__a311oi_2       1
+     sky130_fd_sc_hd__a31o_2        25
+     sky130_fd_sc_hd__a31oi_2        3
+     sky130_fd_sc_hd__a32o_2        10
+     sky130_fd_sc_hd__a41o_2         5
+     sky130_fd_sc_hd__and2_2        70
+     sky130_fd_sc_hd__and2b_2        5
+     sky130_fd_sc_hd__and3_2        61
+     sky130_fd_sc_hd__and3b_2       20
+     sky130_fd_sc_hd__and4_2         8
+     sky130_fd_sc_hd__and4b_2        3
+     sky130_fd_sc_hd__and4bb_2       2
+     sky130_fd_sc_hd__buf_1        294
+     sky130_fd_sc_hd__buf_2          1
+     sky130_fd_sc_hd__conb_1        23
+     sky130_fd_sc_hd__dfxtp_2      326
+     sky130_fd_sc_hd__inv_2         54
+     sky130_fd_sc_hd__mux2_2       210
+     sky130_fd_sc_hd__mux4_2        22
+     sky130_fd_sc_hd__nand2_2       49
+     sky130_fd_sc_hd__nand2b_2       2
+     sky130_fd_sc_hd__nand3_2        6
+     sky130_fd_sc_hd__nand4_2        1
+     sky130_fd_sc_hd__nand4b_2       1
+     sky130_fd_sc_hd__nor2_2       209
+     sky130_fd_sc_hd__nor2b_2        4
+     sky130_fd_sc_hd__nor3_2         3
+     sky130_fd_sc_hd__nor4_2         1
+     sky130_fd_sc_hd__o2111a_2       6
+     sky130_fd_sc_hd__o211a_2       24
+     sky130_fd_sc_hd__o211ai_2       4
+     sky130_fd_sc_hd__o21a_2        26
+     sky130_fd_sc_hd__o21ai_2       59
+     sky130_fd_sc_hd__o21ba_2        6
+     sky130_fd_sc_hd__o21bai_2       3
+     sky130_fd_sc_hd__o221a_2       11
+     sky130_fd_sc_hd__o221ai_2       1
+     sky130_fd_sc_hd__o22a_2        15
+     sky130_fd_sc_hd__o22ai_2        1
+     sky130_fd_sc_hd__o2bb2a_2       4
+     sky130_fd_sc_hd__o311a_2        9
+     sky130_fd_sc_hd__o31a_2        10
+     sky130_fd_sc_hd__o31ai_2        1
+     sky130_fd_sc_hd__o32a_2         3
+     sky130_fd_sc_hd__o41a_2         1
+     sky130_fd_sc_hd__or2_2         46
+     sky130_fd_sc_hd__or2b_2        10
+     sky130_fd_sc_hd__or3_2         16
+     sky130_fd_sc_hd__or3b_2        14
+     sky130_fd_sc_hd__or4_2          9
+     sky130_fd_sc_hd__or4b_2         2
+     sky130_fd_sc_hd__or4bb_2        1
+     sky130_fd_sc_hd__xnor2_2        6
+     sky130_fd_sc_hd__xor2_2         6
+
+   Chip area for module '\tt_um_ccattuto_conway': 18919.395200
+