sdc: cleanup

Signed-off-by: Øyvind Harboe <[email protected]>
The-OpenROAD-Project · Jul 21, 2024 · 4f28239 · 4f28239
1 parent 5d0fb96
commit 4f28239
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Showing 10 changed files with 6 additions and 213 deletions.
diff --git a/BUILD.bazel b/BUILD.bazel
@@ -46,8 +46,7 @@ filegroup(
 filegroup(
     name = "constraints-sram",
     srcs = [
-        "constraints-sram.sdc",
-        ":util",
+        "constraints.sdc",
     ],
     visibility = [":__subpackages__"],
 )
@@ -671,37 +670,6 @@ build_openroad(
         'place': ['PLACE_DENSITY=0.40']}
         )
 
-build_openroad(
-        docker_image = orfs_version,
-        name = "BoomCore",
-        verilog_files=["rtl/BoomCore.sv",
-        "rtl/Arbiter_18.sv",
-        "rtl/CSRFile.sv",
-        "rtl/Arbiter_19.sv",
-        "rtl/BasicDispatcher.sv",
-        "rtl/BranchMaskGenerationLogic.sv",
-        "rtl/DecodeUnit.sv",
-        "rtl/ALUExeUnit.sv",
-        "rtl/ALUExeUnit_2.sv",
-        "rtl/ALUExeUnit_3.sv",
-        "rtl/ALUExeUnit_4.sv",
-        "rtl/ALUExeUnit_5.sv"
-        ] + exeunitsrc + registerreadsrc,
-        macros=["FpPipeline",
-        "IssueUnitCollapsing_1",
-        "IssueUnitCollapsing_2",
-        "Rob",
-        "RenameStage",
-        "RenameStage_1",
-        "RegisterRead_1",
-        "RegisterFileSynthesizable_1"] +
-        execunits,
-        sdc_constraints = ":constraints-top.sdc",
-        stage_args={
-                'floorplan': ['CORE_UTILIZATION=10','MACRO_PLACE_HALO=50 50'],
-                'place': ['PLACE_DENSITY=0.20']}
-        )
-
 boom_tile_small_srams = [
         "tag_array_64x184",
         "tag_array_64x168",
@@ -830,7 +798,7 @@ build_openroad(
         variant="test",
         macros=["tag_array_64x184"],
         io_constraints=":io",
-		sdc_constraints=":constraints-top.sdc",
+		sdc_constraints=":constraints.sdc",
         stage_args={
                 'synth': ['SYNTH_HIERARCHICAL=1'],
                 'floorplan': [

diff --git a/constraints-boomtile.sdc b/constraints-boomtile.sdc
@@ -1,24 +1,10 @@
 set sdc_version 2.0
 
 set clk_period 6500
-
 set clk_name  clock
 set clk_port_name clock
-set clk_in_pct 0.20
-set clk_out_pct 0.2
-
-create_clock -name $clk_name       -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk_port_name]
-set_clock_uncertainty 10 [get_clocks $clk_name]
-
-create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
-set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
-set_clock_latency     1700 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
-
-set clk_port [get_ports $clk_port_name]
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-
-set_input_delay  [expr $clk_period * $clk_in_pct] -clock ${clk_name}_vir $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_out_pct] -clock ${clk_name}_vir [all_outputs]
 
 # Ignore synchronous reset for now.
 set_false_path -from [get_ports reset]
+
+source $env(PLATFORM_DIR)/constraints.sdc
diff --git a/constraints-branchpredictor.sdc b/constraints-branchpredictor.sdc
diff --git a/constraints-chiptop.sdc b/constraints-chiptop.sdc
diff --git a/constraints-dcache.sdc b/constraints-dcache.sdc
diff --git a/constraints-digitaltop.sdc b/constraints-digitaltop.sdc
diff --git a/constraints-l2.sdc b/constraints-l2.sdc
diff --git a/constraints-sram.sdc b/constraints-sram.sdc
diff --git a/constraints-top.sdc b/constraints-top.sdc
diff --git a/constraints.sdc b/constraints.sdc
@@ -1,21 +1,8 @@
 set sdc_version 2.0
 
-set clk_period 1500
-
+set clk_period 6500
 set clk_name  clock
 set clk_port_name clock
-set clk_in_pct 0.20
-set clk_out_pct 0.2
-
-create_clock -name $clk_name       -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk_port_name]
-set_clock_uncertainty 10 [get_clocks $clk_name]
-
-create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
-set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
-set_clock_latency     400 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
 
-set clk_port [get_ports $clk_port_name]
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+source $env(PLATFORM_DIR)/constraints.sdc
 
-set_input_delay  [expr $clk_period * $clk_in_pct] -clock ${clk_name}_vir $non_clock_inputs 
-set_output_delay [expr $clk_period * $clk_out_pct] -clock ${clk_name}_vir [all_outputs]