ci: faster

Signed-off-by: Øyvind Harboe <[email protected]>
The-OpenROAD-Project · Dec 20, 2024 · d341e18 · d341e18
1 parent cde5506
commit d341e18
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Showing 6 changed files with 19 additions and 25 deletions.
diff --git a/BUILD b/BUILD
@@ -110,7 +110,7 @@ LB_VERILOG_FILES = ["test/mock/lb_32x128.sv"]
 orfs_flow(
     name = "lb_32x128",
     arguments = LB_ARGS,
-    mock_area = 0.5,
+    mock_area = 0.90,
     stage_sources = LB_STAGE_SOURCES,
     verilog_files = LB_VERILOG_FILES,
 )
@@ -163,23 +163,17 @@ orfs_run(
 orfs_flow(
     name = "L1MetadataArray",
     abstract_stage = "cts",
-    arguments = FAST_SETTINGS,
+    arguments = FAST_SETTINGS |
+                {
+                    "SDC_FILE": "$(location :test/constraints-top.sdc)",
+                    "SYNTH_HIERARCHICAL": "1",
+                    "CORE_UTILIZATION": "3",
+                    "RTLMP_FLOW": "1",
+                    "CORE_MARGIN": "2",
+                    "MACRO_PLACE_HALO": "30 30",
+                    "PLACE_DENSITY": "0.10",
+                },
     macros = ["tag_array_64x184_generate_abstract"],
-    stage_arguments = {
-        "synth": {
-            "SDC_FILE": "$(location :test/constraints-top.sdc)",
-            "SYNTH_HIERARCHICAL": "1",
-        },
-        "floorplan": {
-            "CORE_UTILIZATION": "3",
-            "RTLMP_FLOW": "1",
-            "CORE_MARGIN": "2",
-            "MACRO_PLACE_HALO": "30 30",
-        },
-        "place": {
-            "PLACE_DENSITY": "0.20",
-        },
-    },
     stage_sources = {
         "synth": [":test/constraints-top.sdc"],
     },
@@ -361,9 +355,9 @@ compile_pip_requirements(
 
 py_binary(
     name = "plot_repair",
-    main = "plot-retiming.py",
     srcs = [
         "plot-retiming.py",
     ],
-    deps = [requirement("matplotlib")]
+    main = "plot-retiming.py",
+    deps = [requirement("matplotlib")],
 )
diff --git a/another/tag_array_64x184.sv b/another/tag_array_64x184.sv
@@ -31,7 +31,7 @@ module tag_array_64x184(
   input  [7:0]   W0_mask
 );
 
-  reg [183:0] Memory[0:1]; // Reduced to 2 rows
+  reg [183:0] Memory[0:0]; // Reduced to 1 rows
   reg         _R0_en_d0;
   reg [5:0]   _R0_addr_d0;
   reg [1:0]   _W0_addr_d0, _R0_addr_d1; // Reduced to 2 bits

diff --git a/check_mock_area.tcl b/check_mock_area.tcl
@@ -18,7 +18,7 @@ proc expect {value a b} {
     exit 1
   }
 }
-expect Width $width 29.105
-expect Height $height 56.61
+expect Width $width 20.366
+expect Height $height 39.133
 
 exec touch $::env(WORK_HOME)/area_ok.txt
diff --git a/test/mock/lb_32x128.sv b/test/mock/lb_32x128.sv
@@ -10,7 +10,7 @@ module lb_32x128(
   input  [127:0] W0_data
 );
 
-  reg [127:0] Memory[0:1]; // Reduced rows to 2
+  reg [127:0] Memory[0:0]; // Reduced rows to 1
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr[4:3] ^ W0_addr[1:0]] <= W0_data; // XORing high and low bits

diff --git a/test/mock/tag_array_64x184.sv b/test/mock/tag_array_64x184.sv
@@ -31,7 +31,7 @@ module tag_array_64x184(
   input  [7:0]   W0_mask
 );
 
-  reg [183:0] Memory[0:1]; // Reduced to 2 rows
+  reg [183:0] Memory[0:0]; // Reduced to 1 rows
   reg         _R0_en_d0;
   reg [5:0]   _R0_addr_d0;
   reg [1:0]   _W0_addr_d0, _R0_addr_d1; // Reduced to 2 bits

diff --git a/test/rtl/data_2048x8.sv b/test/rtl/data_2048x8.sv
@@ -31,7 +31,7 @@ module data_2048x8(
   input  [3:0]  W0_mask
 );
 
-  reg [7:0]  Memory[0:3];  // Reduced to 4 rows
+  reg [7:0]  Memory[0:0];  // Reduced to 1 rows
   reg        _R0_en_d0;
   reg [1:0]  _R0_addr_d0;  // Reduced to 2 bits
   reg [1:0]  _W0_addr_d0;  // Reduced to 2 bits