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Adding final report step. minor cleanups
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tajayi committed Aug 13, 2019
1 parent a239d22 commit 5cc0bac
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Showing 4 changed files with 40 additions and 7 deletions.
10 changes: 7 additions & 3 deletions flow/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@
# DESIGN_CONFIG=./designs/aes_tsmc65lp.mk
# DESIGN_CONFIG=./designs/ariane_tsmc65lp.mk
# DESIGN_CONFIG=./designs/bp_fe_top_tsmc65lp.mk
DESIGN_CONFIG=./designs/cep_tsmc65lp.mk
# DESIGN_CONFIG=./designs/coyote_tsmc65lp.mk
# DESIGN_CONFIG=./designs/dynamic_node_tsmc65lp.mk
# DESIGN_CONFIG=./designs/gcd_tsmc65lp.mk
Expand Down Expand Up @@ -480,8 +479,13 @@ clean_route:
# | _| | || |\ || | ___) | _ || || |\ | |_| |
# |_| |___|_| \_|___|____/|_| |_|___|_| \_|\____|
#
finish: $(RESULTS_DIR)/6_final.gds
finish: $(RESULTS_DIR)/6_final.gds \
$(REPORTS_DIR)/6_final_report.rpt
# ==============================================================================
$(REPORTS_DIR)/6_final_report.rpt:
resizer $(SCRIPTS_DIR)/final_report.tcl \
2>&1 | tee $(LOG_DIR)/6_1_report.log


# Run magic
#-------------------------------------------------------------------------------
Expand All @@ -492,7 +496,7 @@ $(RESULTS_DIR)/6_final.gds: $(MAGIC_TECH_FILE) $(GDS_FILES) $(RESULTS_DIR)/5_rou

clean_finish:
rm -rf $(RESULTS_DIR)/6_final.gds

rm -rf $(REPORTS_DIR)/6_*.rpt



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30 changes: 30 additions & 0 deletions flow/scripts/final_report.tcl
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@@ -0,0 +1,30 @@
# Read liberty files
foreach libFile $::env(LIB_FILES) {
read_liberty $libFile
}


# Read lef def and sdc
read_lef $::env(OBJECTS_DIR)/merged.lef
read_def $::env(RESULTS_DIR)/5_route.def
read_sdc $::env(RESULTS_DIR)/5_route.sdc


log_begin $::env(REPORTS_DIR)/6_final_report.rpt


report_checks -path_delay min
report_checks -path_delay max
report_checks -unconstrained

report_tns
report_wns


report_power

report_design_area

log_end

exit
6 changes: 2 additions & 4 deletions flow/scripts/synth.tcl
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Expand Up @@ -54,8 +54,7 @@ hierarchy -generate tsmc65lp_* o:Q o:QA o:QB \
synth -top $::env(DESIGN_NAME) -flatten

# Optimize the design
opt
opt_clean -purge
opt -purge

# technology mapping of latches
techmap -map $::env(LATCH_MAP_FILE)
Expand All @@ -78,13 +77,12 @@ hilomap -hicell {*}$::env(TIEHI_CELL_AND_PORT) -locell {*}$::env(TIELO_CELL_AND_
setundef -zero

# Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..})
splitnets ; opt
splitnets

# insert buffer cells for pass through wires
insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)

# remove unused cells and wires
clean
opt_clean -purge

# reports
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1 change: 1 addition & 0 deletions flow/test/.gitignore
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@@ -1 +1,2 @@
logs/
parallel.log

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