mpl2: adapt IO clusters to our flow

[AcKoucher]

When ready, will resolve #4867 and close #5669.

Note: Opening as a draft, because there are regression tests to create.

Goals

1. Improve QoR in terms of WL.
2. Ease the life of the annealer for some cases (e.g., sky130hd/uW) that require extreme virtual std cell utilization configurations to converge.
3. Allow switching from old mpl to mpl2 for cases such as sky130hd/chameleon (This will still require clustering work)

Main Changes

Modify IO Clusters

IO clusters that represent bundledIOs created from the pins placed by random PPL are now groups of unplaced IOs with the same constraints based on the following:

• Individual Pin Constraints:

  • If an IO has a constraint region in a certain boundary, it is constrained to that entire boundary.
  • If an IO has no constraint region, it is constrained to all boundaries.

• Global Pins' Constraints (-exclude)

  • If a boundary has more than 70% of its extension blocked, it is considered a blocked boundary for IOs.
    • Clusters connected to pins constrained to a certain blocked boundary A won't be pushed towards A.

What Annealing Sees

• The distance to boundary that represent WL between clusters and IOs only reduces cost when the cluster is inside outline.
• If a cluster/macro M (soft/hard) has a connection with an IO cluster that represents a certain boundary A, the WL of this connection is the minimum distance between M's bundled center pin and A.
• If a cluster/macro M (soft/hard) has a connection with an IO cluster that represents all boundaries, the WL of this connection is the minimum distance between M's bundled center pin and the closest non-blocked boundary.

Collateral Changes

Needed for the Approach to Work

1. Add Cluster support to HardMacro so that SA can check if they are IO clusters' fixed terminals.
2. Make both Soft/HardMacroSACores have access to the PhisycalHierarchical data where the global constraints are now stored.

Blockages for Pin Access

Generated based on a combination of both global and individual pins' constraints:

1. If there are pins constrained to a certain boundary, we'll generate a blockage for that boundary.
2. If there are no pins constrained a boundary A but there are pins constrained to all boundaries, A won't have a pin access blockage. (Specially important so that SA has more freedom).
3. The depth of the blockage is a combination of the extension of IO clusters and std cell area (this can definitely be further improved to consider the IOs density)

Orientation Improvement

When iterating a net, compute HPWL based on the center of the constraint region for each IO instead of its location.

Debug Mode

1. Blocked boundaries are marked with a red X in the center of their extension
2. Draw distance to constraint || closest boundary only when the cluster/macro is inside the outline

[github-actions]

clang-tidy made some suggestions

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy made some suggestions

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"