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Merge pull request #2685 from jeffng-or/at-aes-block-updates
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updated aes-block config based on autotuner results; updated autotune…
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maliberty authored Jan 18, 2025
2 parents b872032 + 1a33b5b commit f71a924
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Showing 5 changed files with 275 additions and 266 deletions.
16 changes: 8 additions & 8 deletions flow/designs/asap7/aes-block/autotuner.json
Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,16 @@
"_SDC_CLK_PERIOD": {
"type": "float",
"minmax": [
100,
300,
600
],
"step": 0
},
"CORE_UTILIZATION": {
"type": "int",
"minmax": [
0,
20
20,
50
],
"step": 1
},
Expand All @@ -35,16 +35,16 @@
"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
"type": "int",
"minmax": [
1,
5
0,
3
],
"step": 1
},
"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
"type": "int",
"minmax": [
1,
5
0,
3
],
"step": 1
},
Expand All @@ -60,7 +60,7 @@
"type": "float",
"minmax": [
0.0,
0.99
0.2
],
"step": 0
},
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13 changes: 10 additions & 3 deletions flow/designs/asap7/aes-block/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.

export ABC_AREA = 1

export CORE_UTILIZATION = 20
export CORE_ASPECT_RATIO = 1
export CORE_UTILIZATION = 27
export CORE_ASPECT_RATIO = 0.867
export CORE_MARGIN = 2
export PLACE_DENSITY = 0.65

Expand All @@ -29,4 +29,11 @@ export PWR_NETS_VOLTAGES =
# The macros are very small so use a smaller halo
export MACRO_PLACE_HALO ?= 5 5

export ROUTING_LAYER_ADJUSTMENT = 0.3
export ROUTING_LAYER_ADJUSTMENT = 0.23

# Parameters from AutoTuner runs
export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 2
export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 1
export CTS_CLUSTER_SIZE = 155
export CTS_CLUSTER_DIAMETER = 248
export PLACE_DENSITY_LB_ADDON = 0.14
2 changes: 1 addition & 1 deletion flow/designs/asap7/aes-block/constraint.sdc
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 400
set clk_period 475
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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