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RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

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T-K-233/RISC-V-Single-Cycle-CPU

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RISC-V Single Cycle CPU

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Notes

  • Single page version can achieve ~300 Hz clock rate on a i7-6700K computer.

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The software Logisim-evoluion is released under the terms of the GNU GENERAL PUBLIC LICENSE (GPL). For your convenience, the jar file is included in this repository in accordance with the redistribution guideline of the GPL-3.0 license agreement.

This project is under MIT License.

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RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

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