== 16 bit custom CPU in VHDL ==
16-bit CPU with 16 registers and a 3-stage pipeline written in VHDL for the Computer Structure I class of 2015-03 Universidad del Norte Colombia
Prototyped in the Altera DE2 board with a Cyclone II processor. Register values are shown in the LCD display of the Altera DE2 board.
Written by Sebastian "Subv" Valle.