Split SystemVerilog, Verilog and VHDL

SublimeText · Oct 9, 2024 · d58fc82 · d58fc82
1 parent c82773d
commit d58fc82
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Showing 23 changed files with 57 additions and 20 deletions.
diff --git a/icons/icons.json b/icons/icons.json
@@ -3198,6 +3198,20 @@
 			}
 		]
 	},
+	"file_type_systemverilog": {
+		"color": "blue",
+		"syntaxes": [
+			{
+				"extensions": [
+					"sv",
+					"svh",
+					"vh"
+				],
+				"name": "Plain Text (SystemVerilog)",
+				"scope": "source.systemverilog"
+			}
+		]
+	},
 	"file_type_taskfile": {
 		"aliases": [
 			{
@@ -3554,7 +3568,6 @@
 		"syntaxes": [
 			{
 				"extensions": [
-					"v",
 					"vlang"
 				],
 				"name": "Plain Text (V)",
@@ -3622,6 +3635,18 @@
 		],
 		"color": "sky"
 	},
+	"file_type_verilog": {
+		"color": "blue",
+		"syntaxes": [
+			{
+				"extensions": [
+					"v"
+				],
+				"name": "Plain Text (Verilog)",
+				"scope": "source.verilog"
+			}
+		]
+	},
 	"file_type_vhdl": {
 		"color": "blue",
 		"syntaxes": [
@@ -3634,24 +3659,6 @@
 				],
 				"name": "Plain Text (VHDL)",
 				"scope": "source.vhdl"
-			},
-			{
-				"extensions": [
-					"sv",
-					"v",
-					"svh",
-					"vh"
-				],
-				"name": "Plain Text (SystemVerilog)",
-				"scope": "source.systemverilog"
-			},
-			{
-				"extensions": [
-					"v",
-					"V"
-				],
-				"name": "Plain Text (Verilog)",
-				"scope": "source.verilog"
 			}
 		]
 	},

diff --git a/icons/multi/file_type_systemverilog.png b/icons/multi/file_type_systemverilog.png
diff --git a/icons/multi/[email protected] b/icons/multi/[email protected]
diff --git a/icons/multi/[email protected] b/icons/multi/[email protected]
diff --git a/icons/multi/file_type_verilog.png b/icons/multi/file_type_verilog.png
diff --git a/icons/multi/[email protected] b/icons/multi/[email protected]
diff --git a/icons/multi/[email protected] b/icons/multi/[email protected]
diff --git a/icons/single/file_type_systemverilog.png b/icons/single/file_type_systemverilog.png
diff --git a/icons/single/[email protected] b/icons/single/[email protected]
diff --git a/icons/single/[email protected] b/icons/single/[email protected]
diff --git a/icons/single/file_type_verilog.png b/icons/single/file_type_verilog.png
diff --git a/icons/single/[email protected] b/icons/single/[email protected]
diff --git a/icons/single/[email protected] b/icons/single/[email protected]
diff --git a/icons/svg/file_type_systemverilog.svg b/icons/svg/file_type_systemverilog.svg
diff --git a/icons/svg/file_type_verilog.svg b/icons/svg/file_type_verilog.svg
diff --git a/preferences/file_type_systemverilog.tmPreferences b/preferences/file_type_systemverilog.tmPreferences
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<plist version="1.0">
+	<dict>
+		<key>scope</key>
+		<string>source.systemverilog</string>
+		<key>settings</key>
+		<dict>
+			<key>icon</key>
+			<string>file_type_systemverilog</string>
+		</dict>
+	</dict>
+</plist>
diff --git a/preferences/file_type_verilog.tmPreferences b/preferences/file_type_verilog.tmPreferences
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<plist version="1.0">
+	<dict>
+		<key>scope</key>
+		<string>source.verilog</string>
+		<key>settings</key>
+		<dict>
+			<key>icon</key>
+			<string>file_type_verilog</string>
+		</dict>
+	</dict>
+</plist>
diff --git a/preferences/file_type_vhdl.tmPreferences b/preferences/file_type_vhdl.tmPreferences
@@ -2,7 +2,7 @@
 <plist version="1.0">
 	<dict>
 		<key>scope</key>
-		<string>source.systemverilog, source.verilog, source.vhdl</string>
+		<string>source.vhdl</string>
 		<key>settings</key>
 		<dict>
 			<key>icon</key>

diff --git a/tests/file_type_v.v → tests/file_type_systemverilog.sv b/tests/file_type_v.v → tests/file_type_systemverilog.sv
diff --git a/tests/file_type_vhdl.sv → tests/file_type_systemverilog.svh b/tests/file_type_vhdl.sv → tests/file_type_systemverilog.svh
diff --git a/tests/file_type_vhdl.svh → tests/file_type_systemverilog.vh b/tests/file_type_vhdl.svh → tests/file_type_systemverilog.vh
diff --git a/tests/file_type_vhdl.v → tests/file_type_verilog.v b/tests/file_type_vhdl.v → tests/file_type_verilog.v
diff --git a/tests/file_type_vhdl.vh b/tests/file_type_vhdl.vh