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Issues list

VexRiscv for custom processing in memory instructions
#420 opened Aug 7, 2024 by neha2351
2
AxiCrossBar with Standard Axi4 Interface in Briey
#406 opened May 6, 2024 by ic-hjx
15
How to only modify certain one reset kind of specific Reg in vex core.
#404 opened Apr 22, 2024 by littlezpf666
1
Exit cycle accurate simulation
#398 opened Mar 12, 2024 by ashuthosh-mr
1
Compile C code and run bare metal cycle accurate simulation
#395 opened Mar 6, 2024 by nachiket
3
EU Funding
#393 opened Mar 1, 2024 by PythonLinks
3
Data Stream in/out SoC <-> FPGA
#391 opened Feb 6, 2024 by lk-davidegironi
6
DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used
#389 opened Feb 4, 2024 by Tahamermer
3
Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.)
#385 opened Dec 15, 2023 by nohahanon
1
debug
#384 opened Dec 12, 2023 by chshux
1
Murax XIP compile issue
#380 opened Nov 24, 2023 by lk-davidegironi
11
compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216
#362 opened Sep 5, 2023 by SoCScholar
1
RiscV Counters
#361 opened Aug 28, 2023 by jjjt-git
1
1
Some documentation on Timer/interrupts
#360 opened Aug 10, 2023 by Jupestrone
1
dev, sim: Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01
#355 opened Jul 16, 2023 by likewise
3
How can with Murax soc connect a memory on apb bus?
#351 opened Jun 25, 2023 by MartinaBarreiroGuerra
3
Axi4Crossbar
#331 opened Apr 15, 2023 by ztachip
1
How can I initial the pipeline registers？
#324 opened Mar 13, 2023 by ZhengJuzhong666
3
How to interface with a VHDL module with Axi4
#311 opened Feb 28, 2023 by cofleury
3
Bug report: wrong sign injection when encountering NaNs
#309 opened Feb 28, 2023 by flaviens
5
RFE: limit cache tag width
#303 opened Feb 23, 2023 by hpax
1
Issues using Eclipse to run and debug the software
#299 opened Feb 13, 2023 by hparpinel
8
RISC-V Vector extensions support
#298 opened Feb 6, 2023 by YiminGao0113
3
Zephyr - new FPU context switch not working in VexRiscV-smp CPU
#297 opened Feb 3, 2023 by pottendo
24
DE1-SOC Quartus Full design synthesis issue
#295 opened Jan 13, 2023 by Light9162
1
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