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[llvm][ARM][NFC] Renaming FeaturePrefLoopAlignment (llvm#109932)
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The feature 'FeaturePrefLoopAlignment' was misleading as it was used to
set the alignment of branch targets such as functions. Renamed to
FeaturePreferfBranchAlignment.
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@nasherm
nasherm authored Sep 26, 2024
1 parent 3eaaf7c commit 439dcfa
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Showing 5 changed files with 20 additions and 17 deletions.
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMFeatures.td
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Original file line number Diff line number Diff line change
Expand Up @@ -372,11 +372,11 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true",
"Prefer 32-bit Thumb instrs">;

def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
"Prefer 32-bit alignment for loops">;
def FeaturePreferBranchAlign32 : SubtargetFeature<"loop-align", "PreferBranchLogAlignment","2",
"Prefer 32-bit alignment for branch targets">;

def FeaturePrefLoopAlign64 : SubtargetFeature<"loop-align-64", "PrefLoopLogAlignment","3",
"Prefer 64-bit alignment for loops">;
def FeaturePreferBranchAlign64 : SubtargetFeature<"branch-align-64", "PreferBranchLogAlignment","3",
"Prefer 64-bit alignment for branch targets">;

def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4",
"Model MVE instructions as a 1 beat per tick architecture">;
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5 changes: 3 additions & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -1635,8 +1635,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// Prefer likely predicted branches to selects on out-of-order cores.
PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();

setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
setPrefFunctionAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
setPrefLoopAlignment(Align(1ULL << Subtarget->getPreferBranchLogAlignment()));
setPrefFunctionAlignment(
Align(1ULL << Subtarget->getPreferBranchLogAlignment()));

setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
}
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16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMProcessors.td
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Expand Up @@ -324,7 +324,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,

def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
ProcM3,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureUseMISched,
FeatureHasNoBranchPredictor]>;

Expand All @@ -335,7 +335,7 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,

def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
FeatureVFP4_D16_SP,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
Expand All @@ -344,7 +344,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
ProcM7,
FeatureFPARMv8_D16,
FeaturePrefLoopAlign64,
FeaturePreferBranchAlign64,
FeatureUseMIPipeliner,
FeatureUseMISched]>;

Expand All @@ -355,7 +355,7 @@ def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
Expand All @@ -365,7 +365,7 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
Expand All @@ -377,7 +377,7 @@ def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline,
FeatureFPARMv8_D16,
FeatureUseMISched,
FeatureHasNoBranchPredictor,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
HasMVEFloatOps,
FeatureFixCMSE_CVE_2021_35465]>;
Expand All @@ -386,7 +386,7 @@ def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline,
FeatureDSP,
FeatureFPARMv8_D16,
FeaturePACBTI,
FeaturePrefLoopAlign64,
FeaturePreferBranchAlign64,
FeatureUseMISched,
HasMVEFloatOps]>;

Expand All @@ -396,7 +396,7 @@ def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline,
FeatureHasNoBranchPredictor,
FeaturePACBTI,
FeatureUseMISched,
FeaturePrefLoopAlign32,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureMVEVectorCostFactor1,
HasMVEFloatOps]>;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMSubtarget.cpp
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Expand Up @@ -302,7 +302,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
LdStMultipleTiming = SingleIssuePlusExtras;
MaxInterleaveFactor = 4;
if (!isThumb())
PrefLoopLogAlignment = 3;
PreferBranchLogAlignment = 3;
break;
case Kryo:
break;
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6 changes: 4 additions & 2 deletions llvm/lib/Target/ARM/ARMSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
int PreISelOperandLatencyAdjustment = 2;

/// What alignment is preferred for loop bodies and functions, in log2(bytes).
unsigned PrefLoopLogAlignment = 0;
unsigned PreferBranchLogAlignment = 0;

/// The cost factor for MVE instructions, representing the multiple beats an
// instruction can take. The default is 2, (set in initSubtargetFeatures so
Expand Down Expand Up @@ -476,7 +476,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
return isROPI() || !isTargetELF();
}

unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
unsigned getPreferBranchLogAlignment() const {
return PreferBranchLogAlignment;
}

unsigned
getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {
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