Merge branch 'master' of http://github.com/skillsurf/systemverilog

asic_flow/input/rtl/full_adder.sv

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+/*
+  This code describes a full_adder circuit
+*/
+module full_adder (
+  input  logic a, b, ci,
+  output logic sum, co
+);
+
+  logic wire_1, wire_2;
+  assign wire_1 = a ^ b;       // bitwise XOR
+  assign wire_2 = wire_1 & ci; // bitwise AND
+
+  wire   wire_3 = a & b;       // bitwise AND
+
+  always_comb begin
+    co  = wire_2 | wire_3;     // bitwise OR
+    sum    = wire_1 ^ ci  ;    // bitwise XOR
+  end
+
+endmodule
+
+module full_adder_2 (
+  input  logic a, b, ci,
+  output logic sum, co
+);
+  assign {co, sum} = a + b + ci;
+endmodule

asic_flow/input/tb/full_adder_tb.sv

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+module full_adder_tb;
+
+  timeunit 10ns; timeprecision 1ns;
+
+  logic a=0, ci=0, b, sum, co; // b != 0, intentional
+
+  full_adder dut (.*);
+
+  initial begin // simulation starts
+    $dumpfile("dump.vcd"); $dumpvars;
+
+    #30 a <= 0; b <= 0; ci <= 0;    
+    #10 a <= 0; b <= 0; ci <= 1;
+
+    #20 a <= 1; b <= 1; ci <= 0;
+    #1  assert ({co,sum} == a+b+ci) 
+          $display ("OK"); 
+          else $error("Not OK");
+
+    #10 a <= 1; b <= 1; ci <= 1;
+    #1  assert (dut.wire_1 == 0) // 1 (xor) 1 = 0 
+          else $error("False. wire_1:%d", dut.wire_1);
+
+    $finish(); // simulation ends
+  end
+endmodule