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Update README.md
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kithminrw authored Jun 9, 2024
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Expand Up @@ -139,3 +139,9 @@ Each example introduces digital design concepts and synthesisable (RTL) & non-sy
- **Verification:**
- Simple testbench: `foreach` loop, `typedef`
- Testbench with classes: virtual class to parametrize functions, streaming operator
-
## License
This project is licensed under the MIT License - see the [LICENSE](https://github.com/SkillSurf/systemverilog/blob/main/LICENSE) file for details
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© SkillSurf 2023

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