Temporary fixup for prefix

build.sbt

@@ -43,13 +43,13 @@ addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.fu
 
 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
 val defaultVersions = Seq(
-  "chisel-iotesters" -> "1.5.0-RC1",
-  "chiseltest" -> "0.3.0-RC1"
-  )
+  "chisel-iotesters" -> "1.4.1+",
+  "chiseltest"  -> "0.2.1+"
+)
 
 libraryDependencies ++= defaultVersions.map { case (dep, ver) =>
   "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", ver) }
 
 scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
 
-javacOptions ++= javacOptionsVersion(scalaVersion.value)
+javacOptions ++= javacOptionsVersion(scalaVersion.value)

src/main/scala/Xim/AXI_Bridge.scala

@@ -33,7 +33,7 @@ class AXI_Bridge(width: Int = 64) extends BlackBox with HasBlackBoxInline {
     }))
     setInline("AXI_Bridge.v",
         s"""
-           module chenguokai_AXI_Bridge
+           module AXI_Bridge
            (
                input         clock,
                input         reset,

src/main/scala/Xim/AddModulePrefix.scala

@@ -1,4 +1,4 @@
-package yourpackage
+package Xim
 
 import firrtl._
 import firrtl.annotations.NoTargetAnnotation
@@ -8,34 +8,34 @@ import firrtl.stage.TransformManager.TransformDependency
 case class ModulePrefixAnnotation(prefix: String) extends NoTargetAnnotation
 
 class AddModulePrefix extends Transform with DependencyAPIMigration {
-
+  
   override def prerequisites: Seq[TransformDependency] = firrtl.stage.Forms.ChirrtlForm
-
+  
   override protected def execute(state: CircuitState): CircuitState = {
     val c = state.circuit
-
+    
     val prefix = state.annotations.collectFirst {
       case ModulePrefixAnnotation(p) => p
     }.get
-
+    
     def onStmt(s: Statement): Statement = s match {
       case DefInstance(info, name, module) =>
         DefInstance(info, name, prefix + module)
       case other =>
         other.mapStmt(onStmt)
     }
-
+    
     def onModule(m: DefModule): DefModule = {
       val newMod = m.mapStmt(onStmt)
       newMod match {
         case Module(info, name, ports, body) =>
           Module(info, prefix + name, ports, body)
-        case other =>
-          other
+        case ExtModule(info, name, ports, defname, params) =>
+          ExtModule(info, prefix+name, ports, defname, params)
       }
     }
     val newCircuit = c.mapModule(onModule)
     state.copy(newCircuit.copy(main = prefix + newCircuit.main))
   }
-
+  
 }

src/test/scala/Xim/SoC_Main.scala

@@ -1,6 +1,7 @@
 package Xim
 
 import chisel3._
+import firrtl.stage.RunFirrtlTransformAnnotation
 
 object SoC_Main_Type_One extends App {
     iotesters.Driver.execute(args, () => new SoC) {