Supervisor level testbench passed

auto_test.py

@@ -1,7 +1,7 @@
 import os
 import re # regular expression
 
-path = "/Users/cgk/ownCloud/课程/一生一芯/ict/riscv-tests/isa/" #the path of compiled risc-v test
+path = "/home/wangns/riscv-tests/isa/" #the path of compiled risc-v test
 
 files= os.listdir(path) # get all file names
 
@@ -13,7 +13,8 @@
         continue
     if  re.match('.*dump', file) != None:
         continue
-    if  re.match('rv64ui-p-', file) != None:
+    #if  re.match('rv64ui-p-', file) != None:
+    if re.match('rv64si-p-supervisor', file) != None:
         ans_files.append(file)
 
 # print(ans_files)
@@ -24,6 +25,6 @@
     print(i, end = '')
     i = i + 1
     print("th test")
-    os.system('/Users/cgk/ownCloud/课程/一生一芯/ict/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-apple-darwin/bin/riscv64-unknown-elf-objcopy -O binary ' + path + file + ' /Users/cgk/ownCloud/课程/一生一芯/ict/test.bin.ori')
-    os.system('/Users/cgk/ownCloud/课程/一生一芯/ict/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-apple-darwin/bin/riscv64-unknown-elf-objcopy -I binary -O binary --reverse-bytes=8 /Users/cgk/ownCloud/课程/一生一芯/ict/test.bin.ori /Users/cgk/ownCloud/课程/一生一芯/ict/test.bin')
+    os.system('riscv64-unknown-elf-objcopy -O binary ' + path + file + ' /home/wangns/test.bin.ori')
+    os.system('riscv64-unknown-elf-objcopy -I binary -O binary --reverse-bytes=8 /home/wangns/test.bin.ori /home/wangns/test.bin')
     os.system('sbt "test:runMain Xim.SoC_Main_Type_Two --backend-name verilator"')

src/main/scala/Xim/AXI_ram.scala

@@ -209,7 +209,8 @@ initial begin
     end
     // mem[0] = 32'h863; mem[1] = 32'h06400093; mem[2] = 32'h00000013; mem[3] = 32'h00000013; mem[4] = 32'h00102023; mem[5] = 32'h00002103;
     // mem[6] = 32'h00f00093; mem[7] = 32'h34101073; mem[8] = 32'h34109073; mem[9] = 32'h34186073; mem[10] = 32'h341020f3;
-    mem_file = $$fopen("/home/wangns/rtt-mbcore/bsp/mb-core/rtthread_reversed.bin", "r");
+    //mem_file = $$fopen("/home/wangns/rtt-mbcore/bsp/mb-core/rtthread_reversed.bin", "r");
+    mem_file = $$fopen("/home/wangns/test.bin", "r");
     $$fread(mem, mem_file);
 end
 

src/main/scala/Xim/CPU_Core.scala

@@ -77,9 +77,9 @@ class CPU_Core(val rv_width: Int = 64, inSOC: Boolean = false) extends Module {
     val PrivModule = Module(new PriviledgeSignal)
     val CSRModule = Module(new CSRSignal)
     PrivModule.io.es_valid := EX_Stage.io.es_inst_valid
-    PrivModule.io.es_ex := EX_Stage.io.ex_valid
-    PrivModule.io.inst_mret := EX_Stage.io.es_inst_mret
-    PrivModule.io.inst_sret := EX_Stage.io.es_inst_sret
+    PrivModule.io.es_ex_work := CSRModule.io.es_ex_work
+    PrivModule.io.mret_work := CSRModule.io.mret_work
+    PrivModule.io.sret_work := CSRModule.io.sret_work
     PrivModule.io.mstatus_mpp := CSRModule.io.mstatus_mpp
     PrivModule.io.sstatus_spp := CSRModule.io.sstatus_spp
     CSRModule.io.priv_level := PrivModule.io.priv_level
@@ -102,10 +102,11 @@ class CPU_Core(val rv_width: Int = 64, inSOC: Boolean = false) extends Module {
     CSRModule.io.Csr_num := EX_Stage.io.csr_number
     EX_Stage.io.csr_read_data := CSRModule.io.csr_read_data
     CSRModule.io.csr_write_data := EX_Stage.io.csr_write_data
-    EX_Stage.io.csr_mtvec := CSRModule.io.csr_mtvec
     EX_Stage.io.csr_timer_int := CSRModule.io.timer_int
     EX_Stage.io.mstatus_tsr := CSRModule.io.mstatus_tsr
-
+    EX_Stage.io.trap_entry := CSRModule.io.trap_entry
+    EX_Stage.io.illegal_csr := CSRModule.io.illegal_csr
+
     val branch_predicter = Module(new branch_pred)
 
     IF_Stage.io.next_branch := branch_predicter.io.IF_next_branch

src/main/scala/Xim/CPU_EX.scala

@@ -64,10 +64,11 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
         val csr_number = Output(UInt(12.W))
         val csr_read_data = Input(UInt(rv_width.W))
         val csr_write_data = Output(UInt(rv_width.W))
-        val csr_mtvec = Input(UInt(rv_width.W))
+        val trap_entry = Input(UInt(rv_width.W))
         val csr_timer_int = Input(UInt(1.W))
         val mstatus_tsr = Input(UInt(1.W))
         val priv_level = Input(UInt(2.W))
+        val illegal_csr = Input(Bool())
     })
 
     val es_valid = RegInit(0.U(1.W))
@@ -85,7 +86,7 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
     io.es_pc := es_pc
 
     val CSR_read_data = Wire(UInt(rv_width.W))
-    val CSR_mtvec = Wire(UInt(rv_width.W))
+    io.ex_target := io.trap_entry
     val CSR_mstatus_tsr = Wire(UInt(1.W))
     val es_csr = Wire(UInt(1.W))
     val timer_int = Wire(UInt(1.W))
@@ -777,7 +778,6 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
       inst_csrrci | inst_csrrs | inst_csrrsi | inst_csrrw | inst_csrrwi
 
     CSR_read_data := io.csr_read_data
-    CSR_mtvec := io.csr_mtvec
     CSR_mstatus_tsr := io.mstatus_tsr
     CSR_mepc := io.mepc
     CSR_sepc := io.sepc
@@ -931,8 +931,6 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
         reg_wdata_s := 0.S
     }
 
-    io.ex_target := CSR_mtvec
-
     val fs_ex_r = RegInit(0.U(1.W))
     val fs_excode_r = RegInit(0.U(rv_width.W))
     when (es_new_instr === 1.U) {
@@ -967,6 +965,8 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
         es_ex := 1.U
     } .elsewhen (es_valid === 1.U && es_write_ex === 1.U) {
         es_ex := 1.U
+    } .elsewhen (es_valid === 1.U && io.illegal_csr) {
+        es_ex := 1.U
     } .otherwise {
         es_ex := 0.U
     }
@@ -998,6 +998,8 @@ class CPU_EX(val rv_width: Int = 64) extends Module {
         } .otherwise {
             es_excode := excode_const.UserTimerInt
         }
+    } .elsewhen (es_valid === 1.U && io.illegal_csr) {
+        es_excode := excode_const.IllegalInstruction
     } .otherwise {
         es_excode := 0.U
     }