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* Merge pull request #99 in CTORISCVFWINFRA/riscv-fw-infrastructure from b-comrv-rtos to master Squashed commit of the following: commit dafd770e5a6cc48824635501255ff6c83636b616 Author: [email protected] <[email protected]> Date: Thu Aug 6 18:04:05 2020 +0300 bug fix: - when context switch in comrv 3 register were missing when saving to task stack from comrv task stack - use D_BIT_MANIPULATION instead of __riscv_bitmanip commit 64d03f9b3bda042d9eb02de8007121b085eda2e2 Merge: 7b5c487 9188aa6 Author: [email protected] <[email protected]> Date: Thu Aug 6 17:12:31 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit 7b5c4877ec840fa14233bcae2bde311c99a62809 Author: [email protected] <[email protected]> Date: Thu Jul 30 20:54:38 2020 +0300 changes: use __riscv_bitmanip define in comrv new whisper version - fix registers and CSRs exposed to the end user commit 9675ce3d03029058a70f1776bb45398ed65ed047 Merge: 371d28f 735067e Author: [email protected] <[email protected]> Date: Thu Jul 30 12:24:21 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit 371d28fe9ce043f3c5e614856cb477b00f0d00d3 Author: [email protected] <[email protected]> Date: Thu Jul 30 11:41:46 2020 +0300 align to llvm fix: I've reported an issue with llvm (07-08-2019): 'riscv inline assembly input operand failure'; this issue was fixed and our llvm has this fix, so I modify the comrv code accordingly. Link to the issue https://bugs.llvm.org/show_bug.cgi?id=42912 commit e1f0cc4a57118b7c5975985cf7a4bc0b64bf0950 Merge: b22329e 09c771a Author: [email protected] <[email protected]> Date: Thu Jul 30 10:44:40 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit b22329eb0e78adf6e084628881b1078aaaba84e4 Merge: 62b3962 27b7600 Author: [email protected] <[email protected]> Date: Tue Jul 28 16:57:48 2020 +0300 merge commit 62b3962936db326de6fcd4c7e91421ec1cb1b30d Author: [email protected] <[email protected]> Date: Tue Jul 28 16:55:37 2020 +0300 new whisper version: whisper version with a fix related to sw interrupt comrv - empty macro for triggering sw interrupt comrv - add missing code (ret) in comrvReset commit 9b066cb9e9ec673ff2a02a3db062a182a1042b85 Merge: fbefee6 46c26ea Author: [email protected] <[email protected]> Date: Tue Jul 28 13:29:22 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit fbefee66960b8a27a3bffdac13c24087be189874 Author: [email protected] <[email protected]> Date: Tue Jul 28 11:57:20 2020 +0300 CR changes: > rename reset function to comrvReset > comrvReset now gets an enum as input add call to comrvReset in the baremetal demo add critical section protection when resetting comrv control block commit 529d475ff7ac3e78dc063e24768271d9e8e44b89 Author: [email protected] <[email protected]> Date: Sun Jul 26 15:55:34 2020 +0300 add reset function comrvResetCacheCB() * Update readme: * Remove support for lagacy Nexys * Remove support for unleashed * Adding support for EH2, EL2 * Adding comments for shallow cloning * adding link to swerfolf * Merge pull request #107 in CTORISCVFWINFRA/riscv-fw-infrastructure from static/bitmanip_eh2_el2_to_master to master * Bitmanip support Squashed commit of the following: commit 2961c33ee2c95ab3f225e98bc91ad8b46cb7c443 Author: nati rapaport <[email protected]> Date: Tue Aug 25 18:30:10 2020 +0300 merge 2 static brances, to get rid of unwanted commit's history * Merge pull request #105 in CTORISCVFWINFRA/riscv-fw-infrastructure from mpmc_haltie_fix_for_ehx1 to master **** Add 'haltie' option in mpmc CSR when setting core to 'Halted' state. Currently demo fails! since there is no HW support **** 'haltie' feature is supported only if SweRV EH1 version is bigger than 0.9 and EH2 Squashed commit of the following: commit ed29a66e3a3ab81180470758c4b9743771f65cac Merge: 88ff9ab 759c8c6 Author: nati rapaport <[email protected]> Date: Tue Sep 1 19:57:22 2020 +0300 Merge branch 'master' into mpmc_haltie_fix_for_ehx1 commit 88ff9ab6a806a3202b8e651fd5b609c16b0b77b8 Author: nati rapaport <[email protected]> Date: Mon Aug 24 14:26:37 2020 +0300 use string D_EHX1_VER_1_0 and D_EHX1_VER_0_9 to distinguish the EHX1 versions commit 5c79f15f8b08a19c36f9f69311585a5c9857d284 Author: nati rapaport <[email protected]> Date: Sun Aug 23 18:51:09 2020 +0300 fix the demo function - disable interrupts before starting the 'haltie' test commit 1b48180a20e29c82dd48a1c1faf51112a53b2e51 Author: nati rapaport <[email protected]> Date: Sun Aug 23 15:08:41 2020 +0300 SweRV EL2 and EH2 are aligned with SweRV EHX1 meaning they both support 'haltie' feature commit 7da73495bc9610346f4c208d0dd323334e07d50c Author: nati rapaport <[email protected]> Date: Sun Aug 23 14:24:24 2020 +0300 'haltie' feature is supported only if SweRV EHX1 version is bigger than 0.9 commit a67755c4b2b01a6e4abc6321538ed18a18c8c40f Author: nati rapaport <[email protected]> Date: Thu Aug 20 11:22:48 2020 +0300 Add 'haltie' option in mpmc CSR when setting core to 'Halted' state. Currently demo fails! * Merge pull request #109 in CTORISCVFWINFRA/riscv-fw-infrastructure from CSRs_updates_SweRV_EL2_EH2 to master ***** Updated CSRs for SweRV EL2 and EH2 Squashed commit of the following: commit 51bfb32e1816d71ea3c9091239042bf89b2c71a1 Author: nati rapaport <[email protected]> Date: Wed Aug 26 15:04:01 2020 +0300 CSRs update for EL2 and EH2 * Merge pull request #102 in CTORISCVFWINFRA/riscv-fw-infrastructure from swerv_2nd_gen_timer_feature to master **** Add 'cascade' feature to 2'nd-gen SweRV **** Disable/restore interrupts upon timers setup (for all SweRV generations) **** Some in-code documentation fixes (for all Cores) Squashed commit of the following: commit e6df7a2478f3ee6e5d4586b9466ecceed40fae0c Merge: 992fa75 71aa66a Author: nati rapaport <[email protected]> Date: Wed Sep 2 15:46:24 2020 +0300 Merge branch 'master' into swerv_2nd_gen_timer_feature commit 992fa75e834bed301a9f53320152030012276f4d Author: nati rapaport <[email protected]> Date: Tue Aug 25 22:59:17 2020 +0300 Address PR remarks commit b5b0227e8a392269688f591a3c89cfe55cba71cd Author: nati rapaport <[email protected]> Date: Wed Aug 19 17:27:35 2020 +0300 enabe/restore interrupts upon timers setup in Swerv-EH1 also commit e90e711a80843bbf340c6795cf3f8f2e1c64ec17 Author: nati rapaport <[email protected]> Date: Wed Aug 19 17:26:08 2020 +0300 Add 'cascade' feature to 2'nd-gen SweRV + enabe/restore interrupts upon timers setup + some in-code documentation fixes * Merge pull request #103 in CTORISCVFWINFRA/riscv-fw-infrastructure from perf_monitor_fix_and_2nd_gen to master *** fix - performance-monitor to supply 64bit of event counters rather only 32bits *** add EL2 and EH2 perf-monitor features Squashed commit of the following: commit 161c54d6872b255b7498cc1ab8fd1a298a950d10 Author: nati rapaport <[email protected]> Date: Thu Sep 3 11:57:51 2020 +0300 some modifications following the merge with master commit f71ca683b3620cc4314efb3264f301c16086fbee Merge: f2c98aa a60ae56 Author: nati rapaport <[email protected]> Date: Thu Sep 3 10:02:11 2020 +0300 Merge branch 'master' into perf_monitor_fix_and_2nd_gen commit f2c98aaf5bd96dd68ae0ef3928339c712baf852c Author: nati rapaport <[email protected]> Date: Wed Sep 2 09:48:15 2020 +0300 Address PR comments - give a 0xDEADBEEF default value to returned perf-mon counter. Locate functions in PSP section commit 430a528561b699b26d21746a67a14f2adf597b4d Author: nati rapaport <[email protected]> Date: Tue Sep 1 12:23:45 2020 +0300 common base of SeRV eh1 aaaaand el2 in the demo function commit 4c008956e72ab9b72f94dae243e98eb2b407abc8 Author: nati rapaport <[email protected]> Date: Mon Aug 31 21:01:12 2020 +0300 modify perf-mon demo to control all counters and to enable/disable all. fix a bug in psp - remove wrong CSR definition of timer counter commit 7cb259f1c01156415b6c95807fe9ca1338548534 Author: nati rapaport <[email protected]> Date: Mon Aug 24 15:43:56 2020 +0300 set/clear all 5 counters in one CSR access rather than 5 accesses commit 35a6fa6d7e2add1b349a452fe714691dac37f3b3 Author: nati rapaport <[email protected]> Date: Mon Aug 24 15:05:59 2020 +0300 Do not #undef.. events from eh1 to eh2 and el2 commit 6a971d8dc519ba3be19e64994e06e7ecd781694d Author: nati rapaport <[email protected]> Date: Thu Aug 20 19:06:05 2020 +0300 add EL2 and EH2 perf-monitor features commit 16f39487694e0b792e7f3b758d367899d5b72baf Author: nati rapaport <[email protected]> Date: Thu Aug 20 16:02:29 2020 +0300 fix - performance-monitor to supply 64bit of event counters rather only 32bits * Merge pull request #108 in CTORISCVFWINFRA/riscv-fw-infrastructure from NMIs_el2_eh2 to master **** NMIs updated features for SweRV EL2 and EH2 Squashed commit of the following: commit 829f2dbac157806285d956a9f4c3feec6693e25c Author: nati rapaport <[email protected]> Date: Thu Sep 3 13:29:01 2020 +0300 modify demo/demo_pwr_mgmt_control.c following merge with master commit 3990c0e4d9a9d11e2072956984d5bede65c28de4 Merge: 90c2d56 67bbb46 Author: nati rapaport <[email protected]> Date: Thu Sep 3 13:27:50 2020 +0300 Merge branch 'master' into NMIs_el2_eh2 commit 90c2d562c8c0d90244f49b0b7ec46c96b9b2cdb2 Merge: e81f63d a60ae56 Author: nati rapaport <[email protected]> Date: Thu Sep 3 12:20:07 2020 +0300 Merge branch 'master' into NMIs_el2_eh2 commit e81f63d2bb57688b6a9e0968a92afe47ec353ab9 Author: nati rapaport <[email protected]> Date: Wed Aug 26 14:40:21 2020 +0300 NMIs changes for EL2 and EH2 * Merge pull request #111 in CTORISCVFWINFRA/riscv-fw-infrastructure from some_cleanup to master *** Add interrupts-vector registration at bitmanip demo start *** Rename psp_bitmanip_eh2.h --> psp_bitmanip_el2.h *** Rename eh2 whisper launcher names to be more clear Squashed commit of the following: commit 3b4257d48f6d76751714a35c8af17e69e6b2ffca Author: nati rapaport <[email protected]> Date: Mon Sep 7 17:18:40 2020 +0300 forgot to commit the eh2 whisper launcher with the new name.. commit bf2e21364e8895379d7953a68093c8fabab5ad47 Author: nati rapaport <[email protected]> Date: Mon Sep 7 16:58:55 2020 +0300 rename psp_bitmanip_eh2.h -> psp_bitmanip_el2.h, add instructions-vector registration at the start of bitmanip demo, rename eh2 whisper launcher names to be clearer * Merge pull request #101 in CTORISCVFWINFRA/riscv-fw-infrastructure from b-comrv-rtos to master *** bug fix in comrv - defragmentation implementation was incorrect; fix was tested with cti *** bug fix in python script - in case a cache entry isn't used, a size of 1 was used for it instead of its real size (fix already pushed to gitlab binutiels) *** in comrv.c rename comrv_ti -> cti Squashed commit of the following: commit 296375be2431d47339d1eb105845e0f92ab362d4 Author: [email protected] <[email protected]> Date: Mon Aug 17 10:47:17 2020 +0300 add CTI defrag mark and rename CTI macros fro D_ to M_ commit 1d305d31dc15259a6625196e6d3634f2f321c01a Author: [email protected] <[email protected]> Date: Sun Aug 16 12:59:58 2020 +0300 bug fix: > bug fix in comrv - defragmentation implementation was incorrect; fix was tested with cti > bug fix in python script - in case a cache entry isn't used, a size of 1 was used for it instead of its real size > in comrv.c rename comrv_ti -> cti commit 99056790ac4bcd77925081fe00b8604caba8dd66 Merge: dafd770 474b4b9 Author: [email protected] <[email protected]> Date: Sun Aug 9 07:32:08 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit dafd770e5a6cc48824635501255ff6c83636b616 Author: [email protected] <[email protected]> Date: Thu Aug 6 18:04:05 2020 +0300 bug fix: - when context switch in comrv 3 register were missing when saving to task stack from comrv task stack - use D_BIT_MANIPULATION instead of __riscv_bitmanip commit 64d03f9b3bda042d9eb02de8007121b085eda2e2 Merge: 7b5c487 9188aa6 Author: [email protected] <[email protected]> Date: Thu Aug 6 17:12:31 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit 7b5c4877ec840fa14233bcae2bde311c99a62809 Author: [email protected] <[email protected]> Date: Thu Jul 30 20:54:38 2020 +0300 changes: use __riscv_bitmanip define in comrv new whisper version - fix registers and CSRs exposed to the end user commit 9675ce3d03029058a70f1776bb45398ed65ed047 Merge: 371d28f 735067e Author: [email protected] <[email protected]> Date: Thu Jul 30 12:24:21 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit 371d28fe9ce043f3c5e614856cb477b00f0d00d3 Author: [email protected] <[email protected]> Date: Thu Jul 30 11:41:46 2020 +0300 align to llvm fix: I've reported an issue with llvm (07-08-2019): 'riscv inline assembly input operand failure'; this issue was fixed and our llvm has this fix, so I modify the comrv code accordingly. Link to the issue https://bugs.llvm.org/show_bug.cgi?id=42912 commit e1f0cc4a57118b7c5975985cf7a4bc0b64bf0950 Merge: b22329e 09c771a Author: [email protected] <[email protected]> Date: Thu Jul 30 10:44:40 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit b22329eb0e78adf6e084628881b1078aaaba84e4 Merge: 62b3962 27b7600 Author: [email protected] <[email protected]> Date: Tue Jul 28 16:57:48 2020 +0300 merge commit 62b3962936db326de6fcd4c7e91421ec1cb1b30d Author: [email protected] <[email protected]> Date: Tue Jul 28 16:55:37 2020 +0300 new whisper version: whisper version with a fix related to sw interrupt comrv - empty macro for triggering sw interrupt comrv - add missing code (ret) in comrvReset commit 9b066cb9e9ec673ff2a02a3db062a182a1042b85 Merge: fbefee6 46c26ea Author: [email protected] <[email protected]> Date: Tue Jul 28 13:29:22 2020 +0300 Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos commit fbefee66960b8a27a3bffdac13c24087be189874 Author: [email protected] <[email protected]> Date: Tue Jul 28 11:57:20 2020 +0300 CR changes: > rename reset function to comrvReset > comrvReset now gets an enum as input add call to comrvReset in the baremetal demo add critical section protection when resetting comrv control block commit 529d475ff7ac3e78dc063e24768271d9e8e44b89 Author: [email protected] <[email protected]> Date: Sun Jul 26 15:55:34 2020 +0300 add reset function comrvResetCacheCB() * README.md edited online with Bitbucket * Merge pull request #112 in CTORISCVFWINFRA/riscv-fw-infrastructure from new-gdb-for-llvm to master *** New GDB for llvm toolchain *** Hash #7f102cf34ac ```tar file was checked using beyond compare with old toolchain/llvm folder``` ```GDB was tested by debugging various scenarios (foo foo tests)``` Squashed commit of the following: commit 7f102cf34ac2aff00581390dad7b0e80f37d0bc9 Author: [email protected] <[email protected]> Date: Tue Sep 8 18:32:41 2020 +0300 new gdb for llvm * Merge pull request #114 in CTORISCVFWINFRA/riscv-fw-infrastructure from software_interrupts_el2_eh2 to master *** Adding Demo for software-interrupts for EL2 and EH2 (currently supported only by Whisper) Squashed commit of the following: commit c2749468472b6269c20a84516d381f7defbeb189 Author: nati rapaport <[email protected]> Date: Wed Sep 9 18:48:55 2020 +0300 simple demo for software-interrupt - el2 & eh2 * rebase from 75231f6 up to 5-Oct ef60b3b0150a596ffb609df22666bff66785b3fb, log history : ------------------------------------------------------------------------------------------------------------------------- Merge pull request #125 in CTORISCVFWINFRA/riscv-fw-infrastructure from merge-llvm-comrv-bitmanip to master *** unified support for one llvm that include comrv and bitmanip. *** the change support scons toolchain change and python change to take the llvm compilation and elfdump *** note: missing parsing by gdb for bitmanip commands. Squashed commit of the following: commit aec346d6a90252a0188e70379168cbc22b14f566 Author: Nidal Faour <[email protected]> Date: Sun Oct 4 17:59:36 2020 +0300 remove unused import commit f933979c600ea637a7ecee81cd8149d60a177a5e Author: Nidal Faour <[email protected]> Date: Sun Oct 4 17:39:46 2020 +0300 remove old bitmanip scons tools commit 5f6e529f6c272f324e23e2f88ed6fbd1fea7537c Author: Nidal Faour <[email protected]> Date: Sun Oct 4 14:50:59 2020 +0300 merging tools between llvm-comrv and llvm-bitmanip commit 7eb9ce8bafaebc8d12f664ba92d879eb95e3a457 Author: Ofer Shinaar <[email protected]> Date: Sun Oct 4 05:20:50 2020 +0000 Merge pull request #122 in CTORISCVFWINFRA/riscv-fw-infrastructure from llvm-clang-12 to master **** new llvm-clang 12 with bitmanip and comrv support riscv-binutils url=https://github.com/westerndigitalcorporation/binutils-gdb.git branch=comrv-devel hash=fdc2b818c6f0c43ae1c76b6aa25fcc2dbae8ba99 riscv-gcc url=https://github.com/gcc-mirror/gcc.git branch=releases/gcc-10.2.0 hash=ee5c3db6c5b2c3332912fb4c9cfa2864569ebd9a riscv-glibc url=https://sourceware.org/git/glibc.git branch=glibc-2.32 hash=3de512be7ea6053255afed6154db9ee31d4e557a riscv-dejagnu url=https://git.savannah.gnu.org/git/dejagnu.git branch=dejagnu-1.6.2-release hash=4b1aeb8672be74417f1b5f6a5683a0cf9071b39b riscv-newlib url=https://github.com/westerndigitalcorporation/newlib.git branch=heads/master hash=c2d6e6f7f6e4cee5db023fa299d5c39d348805ca riscv-gdb url=https://github.com/westerndigitalcorporation/binutils-gdb.git branch=comrv-devel gfdc2b818c6 hash=fdc2b818c6f0c43ae1c76b6aa25fcc2dbae8ba99 qemu url=https://git.qemu.org/git/qemu.git branch=v4.0.0-1854-g57dfc2c4d5 hash=57dfc2c4d51e770ed3f617e5d1456d1e2bacf3f0 libexpat url=https://github.com/libexpat/libexpat.git branch=R_2_2_9-110-g990e3d07 hash=990e3d07eaa127007f9d304a9b4c6ffadc61b1fe Squashed commit of the following: commit c9bb66cff231ce726bdc99e329628a1ed46087c1 Author: Nidal Faour <[email protected]> Date: Tue Sep 29 15:30:15 2020 +0300 adding new llvm commit a560c73b2a0c0bbc7b6a2069b882c27309d77310 Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 11:55:04 2020 +0000 Merge pull request #121 in CTORISCVFWINFRA/riscv-fw-infrastructure from eh2_align_for_rtos to master *** Add rtosal_int_vect_eh2.S file so rtos demos are now built and run for EH2 single-hart on Whisper *** note it was missing from merge #116 d23135c Squashed commit of the following: commit 3e7ab6ee42fc010beac7626f8e1111f6c8e1afdd Author: nati rapaport <[email protected]> Date: Tue Sep 22 12:53:37 2020 +0300 add rtosal_int_vect_eh2.S file commit f70759e31c060db9f2fffaa603c4007e50e117ca Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 09:42:43 2020 +0000 Merge pull request #120 in CTORISCVFWINFRA/riscv-fw-infrastructure from change_md_readme to master *** update readme file Squashed commit of the following: commit 5487b58900ddbaf2e118ce6a0933b533c7de00af Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 06:25:34 2020 +0000 README.md edited online with Bitbucket commit a50b065ea2d6fccbfc60ff15f7ccdabf51b64c84 Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 06:24:42 2020 +0000 README.md edited online with Bitbucket commit e50a855f69d3c6c15011c5d5232a043dfe9d31d6 Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 06:19:11 2020 +0000 README.md edited online with Bitbucket commit d875ea578206910e617226486c58321b23857edb Merge: 543fc5e 72a7eff Author: ofer shinaar <[email protected]> Date: Tue Sep 22 09:17:01 2020 +0300 Merge branch 'change_md_readme' of https://bitbucket.wdc.com/scm/ctoriscvfwinfra/riscv-fw-infrastructure into change_md_readme commit 543fc5ed553c1eff187c8782d4baa0a8e8faeb2a Author: ofer shinaar <[email protected]> Date: Tue Sep 22 09:16:29 2020 +0300 add prog mode png for nexysa7 commit 72a7eff0d21a7e4be64bfe2a083159b1eeaaa3a1 Author: Ofer Shinaar <[email protected]> Date: Tue Sep 22 06:13:34 2020 +0000 README.md edited online with Bitbucket commit a9a032c7642817d16d0dc4908beec30225052fb4 Author: ofer shinaar <[email protected]> Date: Tue Sep 22 09:10:09 2020 +0300 add prog mode png for nexysa7 commit ce26a0a Author: Ofer Shinaar <[email protected]> Date: Tue Sep 15 15:11:01 2020 +0000 Merge pull request #118 in CTORISCVFWINFRA/riscv-fw-infrastructure from fenci_bsp_register_writes to master **** Call FENCI upon any write-access to BSP register Squashed commit of the following: commit c8d313410b63a3cb48976206eaa297e212fe560a Author: nati rapaport <[email protected]> Date: Mon Sep 14 19:29:29 2020 +0300 fenci any write-access to BSP registers commit 07b3ff3 Author: Ronen Haen <[email protected]> Date: Tue Sep 15 06:34:09 2020 +0000 Merge pull request #117 in CTORISCVFWINFRA/riscv-fw-infrastructure from comrv-cache-size-4K-bug-fix to master Squashed commit of the following: commit 7b9b0136f6bc32297c6c84138e5ced5b6e28cd24 Author: [email protected] <[email protected]> Date: Mon Sep 14 15:00:05 2020 +0300 bug fix - remove code which cased corruption of the lru list in ases the cache size contains 2 entries only commit bdc1f7262d258199bdf372a72fd64518aaee6345 Author: [email protected] <[email protected]> Date: Sun Sep 13 18:42:42 2020 +0300 fix the corner case where we have a cache size same as the max group supported - global mru wasn't properly saved commit 1a2e32a Author: Ofer Shinaar <[email protected]> Date: Sun Sep 13 09:47:01 2020 +0000 README.md edited online with Bitbucket remove link to code convention commit 65aacc9 Merge: d23135c 74ac59f Author: Ofer Shinaar <[email protected]> Date: Sun Sep 13 09:32:35 2020 +0000 Merge pull request #113 in CTORISCVFWINFRA/riscv-fw-infrastructure from remove_debug_csrs to master **** Remove debug CSRs from PSP * commit '74ac59feae0f57dc04e3864c6c3a436d039e25ed': remove debug CSRs from PSP commit d23135c Author: Ofer Shinaar <[email protected]> Date: Sun Sep 13 08:52:39 2020 +0000 Merge pull request #116 in CTORISCVFWINFRA/riscv-fw-infrastructure from eh2_single_hart_rtos_supported to master *** Support RTOS on EH2 - single-hart on Whisper only Squashed commit of the following: commit 70fd8d5f7e72f2a0a99d556e021cc90883d4d443 Author: nati rapaport <[email protected]> Date: Thu Sep 10 12:40:55 2020 +0300 EH2 supports RTOS with single-hart configuration commit 683b4e9 Author: Ofer Shinaar <[email protected]> Date: Sun Sep 13 08:49:18 2020 +0000 Merge pull request #115 in CTORISCVFWINFRA/riscv-fw-infrastructure from move-to-gcc-10 to master *** Move to gcc 10.2 with GDB 9.2 riscv-gnu-toolchain url=https://github.com/westerndigitalcorporation/riscv-gnu-toolchain.git branch=gcc-10-2-gdb-9-2 hash=5d25a757bb8626f22862cab884f445d0b855e28e Squashed commit of the following: commit 4ea50e2cfa3f3a1f00dd19e0e698ec2dfff07949 Author: Nidal Faour <[email protected]> Date: Thu Sep 10 12:07:17 2020 +0300 moving to gcc 10 & gdb 9.2 ------------------------------------------------------------------------------------------------------------------------- * add hash files * add cti support * upload prog_mode.png, was removed from rebase * add cti files+ latest ovlymgr.py * auto select llvm in case cti demo is configured * Merge pull request #128 in CTORISCVFWINFRA/riscv-fw-infrastructure from new_el2_swervolf_after_rebase to master **** New SweRV EL2 FPGA support new EL2 build without fast-int Squashed commit of the following: commit 4525bdd80a45695e1cfa1ea43a737a3875506956 Author: nati rapaport <[email protected]> Date: Mon Oct 5 14:47:23 2020 +0300 fix README typos commit 0965c8497e07ea7021693b8fad73f58459d200f9 Author: nati rapaport <[email protected]> Date: Mon Oct 5 14:18:02 2020 +0300 New SweRV EL2 FPGA + modify bsp_printf + align pwr-mngmnt demo+ update README file * Merge pull request #129 in CTORISCVFWINFRA/riscv-fw-infrastructure from is_whisper_after_rebase to master *** Check if Swerv or Whisper and run only if demo is supported relevant to SW-interrupts, ext-interrupts, performance-monitor, power-management, NMI, bit-manipulation and cache-control for now.... Squashed commit of the following: commit 0bd81a33d6cd707f74ea2b01d1b8f9a489d69075 Author: nati rapaport <[email protected]> Date: Mon Oct 5 17:23:57 2020 +0300 for clarity sake - specify Swerv FPGA Board, rather than merely SweRV commit 9bf32388aae90869594ec1148107a885ba417fdc Author: nati rapaport <[email protected]> Date: Mon Oct 5 15:54:33 2020 +0300 Check if Swerv or Whisper and run only if demo is supported * add code to verify we run on whisper only * Merge pull request #130 in CTORISCVFWINFRA/riscv-fw-infrastructure from fix-h51-build to master *** fix hifive1 build issue enclose with #ifdef the content of demoIsSwervBoard() function so function won't compile under hifive1 remove eh2 from external interrupts demo as it isn't supported Tested comrv_baremetal, external_interrupts Squashed commit of the following: commit b265a1f632135bc8262c34a1232ce3529fc770bc Author: [email protected] <[email protected]> Date: Tue Oct 6 08:34:58 2020 +0300 fix hifive1 build issue: enclose with #ifdef the content of demoIsSwervBoard() function so function won't compile under hifive1 remove eh2 from external interrupts demo as it isn't supported * Merge pull request #131 in CTORISCVFWINFRA/riscv-fw-infrastructure from hash-update to master **** adding hashes of the gcc in the llvm toolchain. Squashed commit of the following: commit 71c209e29e7b7726dedb1eb4821a33afa6c791a0 Author: Nidal Faour <[email protected]> Date: Tue Oct 6 12:23:48 2020 +0300 fixing branches names in hash, need to fix the script to get the correct branches names, and need to update the tars with the correct branches names. in the gcc need to run the hash script and not create it manually commit a1028d1ea5b354761b450b8b99dcab08e03fa227 Author: Nidal Faour <[email protected]> Date: Tue Oct 6 12:12:05 2020 +0300 adding the gnu hashes to llvm hashes file * add '-Wl' for linker script arg '-T'; now we can use comrv --defsym symbols (__comrv_cache_size, __comrv_cache_alignment_size and __comrv_overlay_storage_size) in a generic manner in all linker scripts * Merge pull request #132 in CTORISCVFWINFRA/riscv-fw-infrastructure from fix-mapfile-sum-tbl to master ****riscv32-unknown-elf-size got a wrnog input for elf name - this fix provides the correct elf name as input Squashed commit of the following: commit 0c9ce3a6e000973642a51b7d8e30503231c74119 Author: [email protected] <[email protected]> Date: Wed Oct 7 10:13:34 2020 +0300 riscv32-unknown-elf-size got a wrog input for elf name - this fix provides the correct elf name as input * Merge pull request #133 in CTORISCVFWINFRA/riscv-fw-infrastructure from update_readme to master *** update readme file and add picture of nexys-a7 Squashed commit of the following: commit e715ae6c30900242d75f5442d10697fa8a10ad79 Author: ofer shinaar <[email protected]> Date: Thu Oct 8 10:39:02 2020 +0300 add image of nexys-a7 board and add comment about sw0 commit 3b786059519844e41e9d552c2ba8d9d81d9db956 Merge: 2869594 7ced70c Author: ofer shinaar <[email protected]> Date: Thu Oct 8 10:36:49 2020 +0300 Merge branch 'update_readme' of https://bitbucket.wdc.com/scm/ctoriscvfwinfra/riscv-fw-infrastructure into update_readme commit 2869594605a2ac61bd621ac5f7df55324527a321 Author: ofer shinaar <[email protected]> Date: Thu Oct 8 10:35:48 2020 +0300 add image of nexys-a7 board and add comment about sw0 commit 7ced70c09606ddc151960136f641d6a620a908ed Author: Ofer Shinaar <[email protected]> Date: Thu Oct 8 07:25:44 2020 +0000 README.md edited online with Bitbucket commit 371ee3e132594362256aa0e0aa3aab8a776a0b78 Author: Ofer Shinaar <[email protected]> Date: Thu Oct 8 07:24:23 2020 +0000 README.md edited online with Bitbucket commit 080c76db3b15d5ecccbf078b1a3720ec9981df6d Author: ofer shinaar <[email protected]> Date: Thu Oct 8 10:21:23 2020 +0300 add image of nexys-a7 board and add comment about sw0 * remove spaces in some *.lds * minor changes following review * rename files * typo - infrastructute -> infrastructure * typos * in build, modify path arguments to be more robust * Merge pull request #135 in CTORISCVFWINFRA/riscv-fw-infrastructure from psp_machine to master **** Machine mode assurance in PSP **** 1. Add 'machine' label to all PSP api's that relevant to M-mode only. 2. Add safe-guards in PSP sensitive functions (like ISR, exp, nmi registrations etc) to make sure they work only in M-mode Squashed commit of the following: commit dd91536ee24eac0a887f8fd61225e596d0f7d6e5 Author: nati rapaport <[email protected]> Date: Thu Oct 15 19:52:28 2020 +0300 remove elx2s from sconstruct commit e4cb9fba54fb2afa4995fe778b139c8a66bcaf03 Author: nati rapaport <[email protected]> Date: Thu Oct 15 10:09:47 2020 +0300 create common macro to assure machine mode commit e94278e8b29a31118707e828f556ad52ae2b9096 Author: nati rapaport <[email protected]> Date: Thu Oct 15 09:15:56 2020 +0300 fix PR following notes commit 5c9e63ee1e94f46df584decc53785aa83d8d994f Author: nati rapaport <[email protected]> Date: Wed Oct 14 18:16:13 2020 +0300 Add 'machine' label to all PSP api's that relevant to M-mode only. Add safe-gurd in PSP sensitive functions (like ISR registrations etc) to make sure they work only in M-mode * Merge pull request #134 in CTORISCVFWINFRA/riscv-fw-infrastructure from some_interrupts_additions to master **** adding new apis * get_exception_handler api * set-mepc-to-next-instruction Squashed commit of the following: commit f562ebf0c60c49b2f653b97007eef51dda498878 Merge: f73ab48 a651c58 Author: nati rapaport <[email protected]> Date: Mon Oct 19 16:12:38 2020 +0300 Merge branch 'master' into some_interrupts_additions commit f73ab48d30c54fc81de2a501122b4152bc101309 Author: nati rapaport <[email protected]> Date: Mon Oct 12 12:34:51 2020 +0300 For coding conventions - rename pspInterruptHandler_t --> fptrInterruptHandler_t commit 029c5ac90281ae1ef3fb785e3433eb5ff6e43f01 Merge: c05a0fd ddf887e Author: nati rapaport <[email protected]> Date: Mon Oct 12 09:52:37 2020 +0300 Merge branch 'master' into some_interrupts_additions commit c05a0fd5d20c040b5cce268a28d494a372cd2857 Author: nati rapaport <[email protected]> Date: Sun Oct 11 18:29:55 2020 +0300 get_exception_handler api, set-mepc-to-next-instruction - these are needed specifically for swerv-elx2s but aded as part of common swerv psp * Merge pull request #140 in CTORISCVFWINFRA/riscv-fw-infrastructure from comrv-bug-fix-invalid-crc-result to master Squashed commit of the following: commit eb1a18cbee3019a30ce22d027a0efcedef03ebbc Author: [email protected] <[email protected]> Date: Tue Nov 10 15:05:09 2020 +0200 bug fix: CRC calculation was wrong if a BP is set in an overlay function before the actual group was loaded. The actual fix is to move the gdb debug symbol location to be after CRC check * added a demo from riscfree presentation * remove hifive-un from comrv demos * README.md edited online with Bitbucket * README.md edited online with Bitbucket * README.md edited online with Bitbucket * Merge pull request #146 in CTORISCVFWINFRA/riscv-fw-infrastructure from fencei_following_mrac_in_startup to master *************** Per SweRV eh1, eh2 and el2 PRMs, fence.i should be done following mrac update Squashed commit of the following: commit 9db4e0a7fe3a0dc8406ffd1cd97f8a6e45068813 Author: nati rapaport <[email protected]> Date: Wed Nov 18 17:47:45 2020 +0200 add fence.i after mrac update in startup.S code * Merge pull request #153 in CTORISCVFWINFRA/riscv-fw-infrastructure from aligned_memory_access to master ************* Change access to memory (using byte access) to overcome issues of 4byte alignment on different cores (sometimes its allowed and sometimes its does not) ** The changes are in BSP on ext-interrupts generation, and in getting FPGA version ** FPGA bit-file loading launcher script for SweRV EL2 has been moved from eh1 path to el2 path Squashed commit of the following: commit f69031650fd407b522e44d575a22fa2dbaf0b798 Author: nati rapaport <[email protected]> Date: Mon Nov 30 12:17:58 2020 +0200 Add PSP macro of 8-bits memory-access. Use it in ext-interrupts generation at from BSP, and in getting FPGA version * Merge pull request #154 in CTORISCVFWINFRA/riscv-fw-infrastructure from mscause_csr to master *********** ** Fix 8-bit access in timer-routing set Squashed commit of the following: commit 8514ef83bc45087c9bf45df3e35c79c7abbc2ba0 Author: nati rapaport <[email protected]> Date: Mon Nov 30 19:16:13 2020 +0200 Add mscause CSR to 2'nd gen cores exception handler. Fix 8-bit access in timer-routing set * Merge pull request #156 in CTORISCVFWINFRA/riscv-fw-infrastructure from new-whisper to master ************* * new whisper to fix 2 gdb sessions Squashed commit of the following: commit ca9d0206831e3e9347b46b596bc00af20e8e1dfd Author: [email protected] <[email protected]> Date: Sun Dec 6 15:14:27 2020 +0200 new whisper version * Merge pull request #155 in CTORISCVFWINFRA/riscv-fw-infrastructure from llvm-release-06-12 to master *** New llvm with gdb fix Squashed commit of the following: commit 5fd5e8d089f2c42f27d3037ceee2c5d627fe9641 Author: Nidal Faour <[email protected]> Date: Sun Dec 6 16:37:50 2020 +0200 adding header to python script commit 3062b82b93124777c4e233a19e03aa9f36db94bf Author: Nidal Faour <[email protected]> Date: Sun Dec 6 12:50:33 2020 +0200 adding the latest overlay manager python script for GDB commit 7b8f86fb735f9092cdda345d647a8c3ea5d10877 Author: Nidal Faour <[email protected]> Date: Sun Dec 6 12:35:15 2020 +0200 adding download links commit 187c646be9cd41b8400d839f3c7f358c1d0c285b Author: Nidal Faour <[email protected]> Date: Sun Dec 6 12:18:39 2020 +0200 updating llvm toolchain - bug fixes Co-authored-by: Ronen Haen <[email protected]>
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