FSM Sequence Detector (110) using Cadence Virtuoso

This project implements a 3-bit sequence detector (detecting 110) using a Mealy Finite State Machine (FSM) in Cadence Virtuoso.
The FSM is built using True Single Phase Clock (TSPC) D Flip-Flops for high-speed performance.

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🔧 Project Description

• Detects binary sequence: 110
• FSM Type: Mealy
• Implemented using logic derived from truth tables and K-maps
• Constructed using TSPC D flip-flops
• Simulated using Spectre in Cadence Virtuoso
• Verified with transient and DC analysis

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🧠 FSM Design Summary

• States: S0 → S1 → S2 → S3 (using 2 flip-flops)
• Output Y becomes 1 when sequence 110 is detected
• DA, DB, and Y expressions derived using Boolean minimization

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BLOCK DIAGRAM

🛠️ Project Contents

Image Preview	Description
📷 FSM Schematic	FSM logic schematic
📷 TSPC D Flip-Flops	TSPC D flip-flops schematic
📷 Symbol View	Custom symbol created for FSM
📷 Testbench	Testbench schematic with clock and input
📷 Waveform Output	Simulation waveform showing detection
📷 State Diagram	FSM state diagram
📷 Truth Table + K-Map	Truth table and K-map simplification
📷 Boolean Equations	Boolean logic equations

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🧪 Simulation Setup

🔁 Clock Source (VPULSE)

Parameter	Value
V1 (Low)	0V
V2 (High)	1V
Period	2ns
Rise/Fall Time	50ps
Pulse Width	1ns

🔁 Input Pulse (VPULSE)

Parameter	Value
V1 (Low)	0V
V2 (High)	1V
Period	6ns
Rise/Fall Time	50ps
Pulse Width	1ns
Delay	500ps

🔋 VDC Supply

Parameter	Value
DC Voltage	1V

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✅ Output Verification

• The output Y goes HIGH as soon as the sequence 110 is detected.
• Simulation waveform confirms correct FSM behavior.

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📸 Screenshots

FSM Schematic	Waveform Output
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⚙️ Tools Used

• Cadence Virtuoso 6.1.8
• Spectre (for transient & DC analysis)
• Linux environment

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🧠 Insights Gained

• FSM Design (Mealy machine)
• K-map simplification for logic expressions
• Schematic and Symbol creation in Cadence
• Transient simulation and waveform analysis
• Working with TSPC D flip-flops for low-power, high-speed design

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🔮 Future Work

• Add layout view with DRC/LVS verification
• Include power and delay analysis using Spectre
• RTL version in Verilog for FPGA comparison
• Implement using FinFET PDK for scaled power analysis

✍️ Author

SURIYA R K - BE EEE

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