fix(cpus): workaround for Cortex-X4 erratum 2701112

Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do not use an Arm interconnect IP.

The workaround for this erratum is not implemented in EL3.
The erratum can be enabled/disabled on a platform level.
The flag is used when the errata ABI feature is enabled and can
assist the Kernel in the process of mitigation of the erratum.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b
Signed-off-by: Sona Mathew <[email protected]>
(cherry picked from commit cc41b56)

docs/design/cpu-specific-build-macros.rst

@@ -816,6 +816,16 @@ For Cortex-X3, the following errata build flags are defined :
   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
   CPU. It is fixed in r1p2.
 
+For Cortex-X4, the following errata build flags are defined :
+
+- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4
+  CPU and affects system configurations that do not use an Arm interconnect IP.
+  This needs to be enabled for revisions r0p0 and is fixed in r0p1.
+  The workaround for this erratum is not implemented in EL3, but the flag can
+  be enabled/disabled at the platform level. The flag is used when the errata ABI
+  feature is enabled and can assist the Kernel in the process of
+  mitigation of the erratum.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

lib/cpus/cpu-ops.mk

@@ -818,6 +818,11 @@ CPU_FLAG_LIST += ERRATA_X3_2743088
 # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2779509
 
+# Flag to apply erratum 2701112 workaround for platforms that do not use an
+# Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4
+# cpu and is fixed in r0p1.
+CPU_FLAG_LIST += ERRATA_X4_2701112
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_A510_1922240

plat/arm/board/fvp/fvp_cpu_errata.mk

@@ -16,13 +16,15 @@ CORTEX_A78_H_INC	:= 1
 CORTEX_A78_AE_H_INC	:= 1
 CORTEX_A78C_H_INC	:= 1
 CORTEX_X3_H_INC		:= 1
+CORTEX_X4_H_INC		:= 1
 NEOVERSE_N2_H_INC	:= 1
 NEOVERSE_V1_H_INC	:= 1
 $(eval $(call add_define, CORTEX_A710_H_INC))
 $(eval $(call add_define, CORTEX_A78_H_INC))
 $(eval $(call add_define, CORTEX_A78_AE_H_INC))
 $(eval $(call add_define, CORTEX_A78C_H_INC))
 $(eval $(call add_define, CORTEX_X3_H_INC))
+$(eval $(call add_define, CORTEX_X4_H_INC))
 $(eval $(call add_define, NEOVERSE_N2_H_INC))
 $(eval $(call add_define, NEOVERSE_V1_H_INC))
 endif

plat/arm/board/fvp/platform.mk

@@ -211,6 +211,7 @@ else
 					lib/cpus/aarch64/neoverse_v1.S		\
 					lib/cpus/aarch64/neoverse_e1.S		\
 					lib/cpus/aarch64/cortex_x2.S		\
+					lib/cpus/aarch64/cortex_x4.S		\
 					lib/cpus/aarch64/cortex_gelas.S		\
 					lib/cpus/aarch64/nevis.S		\
 					lib/cpus/aarch64/travis.S

services/std_svc/errata_abi/cpu_errata_info.h

@@ -17,6 +17,7 @@
 #include <cortex_a78c.h>
 #include <cortex_x2.h>
 #include <cortex_x3.h>
+#include <cortex_x4.h>
 #include <neoverse_n2.h>
 #include <neoverse_v1.h>
 #include <neoverse_v2.h>

services/std_svc/errata_abi/errata_abi_main.c

@@ -111,6 +111,16 @@ struct em_cpu_list cpu_list[] = {
 },
 #endif /* CORTEX_X3_H_INC */
 
+#if CORTEX_X4_H_INC
+{
+	.cpu_partnumber = CORTEX_X4_MIDR,
+	.cpu_errata_list = {
+		[0] = {2701112, 0x00, 0x00},
+		[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+	}
+},
+#endif /* CORTEX_X4_H_INC */
+
 };
 
 #if ERRATA_NON_ARM_INTERCONNECT