vm: update to AluVM supporting strict encoding

RGB-WG · Apr 9, 2024 · 21a9c86 · 21a9c86
1 parent 3508e6e
commit 21a9c86
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Showing 5 changed files with 29 additions and 25 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -63,8 +63,13 @@ wasm-bindgen-test = "0.3"
 features = ["all"]
 
 [patch.crates-io]
+strict_encoding_derive = { git = "https://github.com/strict-types/strict-encoding", branch = "rstring" }
+strict_encoding = { git = "https://github.com/strict-types/strict-encoding", branch = "rstring" }
+strict_types = { git = "https://github.com/strict-types/strict-types", branch = "rstring" }
+commit_verify = { git = "https://github.com/LNP-BP/client_side_validation", branch = "v0.11" }
+single_use_seals = { git = "https://github.com/LNP-BP/client_side_validation", branch = "v0.11" }
 bp-consensus = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
 bp-dbc = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
 bp-seals = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
 bp-core = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
-aluvm = { git = "https://github.com/AluVM/rust-aluvm", branch = "simplify" }
+aluvm = { git = "https://github.com/AluVM/rust-aluvm", branch = "v0.11" }
diff --git a/src/vm/isa.rs b/src/vm/isa.rs
@@ -25,7 +25,7 @@ use std::ops::RangeInclusive;
 
 use aluvm::isa;
 use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
-use aluvm::library::{CodeEofError, LibSite, Read, Write};
+use aluvm::library::{CodeEofError, IsaSeg, LibSite, Read, Write};
 use aluvm::reg::{CoreRegs, Reg};
 
 use super::{ContractOp, TimechainOp};
@@ -48,9 +48,7 @@ pub enum RgbIsa {
 impl InstructionSet for RgbIsa {
     type Context<'ctx> = OpInfo<'ctx>;
 
-    fn isa_ids() -> BTreeSet<&'static str> {
-        bset! {"RGB"}
-    }
+    fn isa_ids() -> IsaSeg { IsaSeg::with("RGB") }
 
     fn src_regs(&self) -> BTreeSet<Reg> {
         match self {

diff --git a/src/vm/op_contract.rs b/src/vm/op_contract.rs
@@ -26,7 +26,7 @@ use std::collections::BTreeSet;
 use std::ops::RangeInclusive;
 
 use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
-use aluvm::library::{CodeEofError, LibSite, Read, Write};
+use aluvm::library::{CodeEofError, IsaSeg, LibSite, Read, Write};
 use aluvm::reg::{CoreRegs, Reg, Reg16, Reg32, RegA, RegS};
 use amplify::num::{u3, u4};
 use amplify::Wrapper;
@@ -156,7 +156,7 @@ pub enum ContractOp {
 impl InstructionSet for ContractOp {
     type Context<'ctx> = OpInfo<'ctx>;
 
-    fn isa_ids() -> BTreeSet<&'static str> { none!() }
+    fn isa_ids() -> IsaSeg { IsaSeg::with("RGB") }
 
     fn src_regs(&self) -> BTreeSet<Reg> {
         match self {
@@ -586,9 +586,9 @@ impl Bytecode for ContractOp {
 
 #[cfg(test)]
 mod test {
-    use aluvm::data::encoding::Encode;
     use aluvm::library::Lib;
     use amplify::hex::ToHex;
+    use strict_encoding::StrictSerialize;
 
     use super::*;
     use crate::vm::RgbIsa;
@@ -597,14 +597,21 @@ mod test {
     fn encoding() {
         let code = [RgbIsa::Contract(ContractOp::PcVs(AssignmentType::from(4000)))];
         let alu_lib = Lib::assemble(&code).unwrap();
+        eprintln!("{alu_lib}");
         let alu_id = alu_lib.id();
 
         assert_eq!(
             alu_id.to_string(),
-            "urn:ubideco:alu:AXicg5WYSF3R36coefDodDX2owpSaZJgco7PHMj8qwiv#china-chant-triton"
+            "urn:ubideco:alu:Bitw9SnAnKhEyuwjjAgM1pLtnvQfQiE8y9NLPAxcXd64#miami-minute-next"
         );
         assert_eq!(alu_lib.code.as_ref().to_hex(), "d0a00f");
-        assert_eq!(alu_lib.serialize().to_hex(), "035247420300d0a00f000000");
+        assert_eq!(
+            alu_lib
+                .to_strict_serialized::<{ usize::MAX }>()
+                .unwrap()
+                .to_hex(),
+            "035247420300d0a00f000000"
+        );
         assert_eq!(alu_lib.disassemble::<RgbIsa>().unwrap(), code);
     }
 }
diff --git a/src/vm/op_timechain.rs b/src/vm/op_timechain.rs
@@ -24,7 +24,7 @@ use std::collections::BTreeSet;
 use std::ops::RangeInclusive;
 
 use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
-use aluvm::library::{CodeEofError, LibSite, Read, Write};
+use aluvm::library::{CodeEofError, IsaSeg, LibSite, Read, Write};
 use aluvm::reg::{CoreRegs, Reg};
 
 use crate::vm::opcodes::{INSTR_TIMECHAIN_FROM, INSTR_TIMECHAIN_TO};
@@ -41,7 +41,7 @@ pub enum TimechainOp {
 impl InstructionSet for TimechainOp {
     type Context<'ctx> = ();
 
-    fn isa_ids() -> BTreeSet<&'static str> { none!() }
+    fn isa_ids() -> IsaSeg { IsaSeg::with("RGB") }
 
     fn src_regs(&self) -> BTreeSet<Reg> { bset![] }