The parameter idle_wires default flipped to False in all circuit drawers

qiskit/circuit/quantumcircuit.py

@@ -3282,9 +3282,9 @@ def draw(
                 will take less vertical room.  Default is ``medium``. Only used by
                 the ``text`` output, will be silently ignored otherwise.
             idle_wires: Include idle wires (wires with no circuit elements)
-                in output visualization. Default is ``True`` unless the
+                in output visualization. Default is ``False`` unless the
                 user config file (usually ``~/.qiskit/settings.conf``) has an
-                alternative value set. For example, ``circuit_idle_wires = False``.
+                alternative value set. For example, ``circuit_idle_wires = True``.
             with_layout: Include layout information, with labels on the
                 physical layout. Default is ``True``.
             fold: Sets pagination. It can be disabled using -1. In ``text``,

qiskit/visualization/circuit/circuit_visualization.py

@@ -142,9 +142,9 @@ def circuit_drawer(
             will take less vertical room.  Default is ``medium``. Only used by
             the ``text`` output, will be silently ignored otherwise.
         idle_wires: Include idle wires (wires with no circuit elements)
-            in output visualization. Default is ``True`` unless the
+            in output visualization. Default is ``False`` unless the
             user config file (usually ``~/.qiskit/settings.conf``) has an
-            alternative value set. For example, ``circuit_idle_wires = False``.
+            alternative value set. For example, ``circuit_idle_wires = True``.
         with_layout: Include layout information, with labels on the
             physical layout. Default is ``True``.
         fold: Sets pagination. It can be disabled using -1. In ``text``,
@@ -205,7 +205,7 @@ def circuit_drawer(
     # Get default from config file else use text
     default_output = "text"
     default_reverse_bits = False
-    default_idle_wires = config.get("circuit_idle_wires", True)
+    default_idle_wires = config.get("circuit_idle_wires", False)
     if config:
         default_output = config.get("circuit_drawer", "text")
         if default_output == "auto":
@@ -368,7 +368,7 @@ def _text_circuit_drawer(
     plot_barriers=True,
     justify=None,
     vertical_compression="high",
-    idle_wires=True,
+    idle_wires=False,
     with_layout=True,
     fold=None,
     initial_state=True,
@@ -388,7 +388,7 @@ def _text_circuit_drawer(
             the circuit should be justified.
         vertical_compression (string): `high`, `medium`, or `low`. It merges the
             lines so the drawing will take less vertical room. Default is `high`.
-        idle_wires (bool): Include idle wires. Default is True.
+        idle_wires (bool): Include idle wires. Default is False.
         with_layout (bool): Include layout information with labels on the physical
             layout. Default: True
         fold (int): Optional. Breaks the circuit drawing to this length. This
@@ -459,7 +459,7 @@ def _latex_circuit_drawer(
     plot_barriers=True,
     reverse_bits=False,
     justify=None,
-    idle_wires=True,
+    idle_wires=False,
     with_layout=True,
     initial_state=False,
     cregbundle=None,
@@ -480,7 +480,7 @@ def _latex_circuit_drawer(
             circuit. Defaults to True.
         justify (str) : `left`, `right` or `none`. Defaults to `left`. Says how
             the circuit should be justified.
-        idle_wires (bool): Include idle wires. Default is True.
+        idle_wires (bool): Include idle wires. Default is False.
         with_layout (bool): Include layout information, with labels on the physical
             layout. Default: True
         initial_state (bool): Optional. Adds |0> in the beginning of the line.
@@ -578,7 +578,7 @@ def _generate_latex_source(
     reverse_bits=False,
     plot_barriers=True,
     justify=None,
-    idle_wires=True,
+    idle_wires=False,
     with_layout=True,
     initial_state=False,
     cregbundle=None,
@@ -597,7 +597,7 @@ def _generate_latex_source(
             circuit. Defaults to True.
         justify (str) : `left`, `right` or `none`. Defaults to `left`. Says how
             the circuit should be justified.
-        idle_wires (bool): Include idle wires. Default is True.
+        idle_wires (bool): Include idle wires. Default is False.
         with_layout (bool): Include layout information, with labels on the physical
             layout. Default: True
         initial_state (bool): Optional. Adds |0> in the beginning of the line.
@@ -651,7 +651,7 @@ def _matplotlib_circuit_drawer(
     plot_barriers=True,
     reverse_bits=False,
     justify=None,
-    idle_wires=True,
+    idle_wires=False,
     with_layout=True,
     fold=None,
     ax=None,
@@ -675,7 +675,7 @@ def _matplotlib_circuit_drawer(
             circuit. Defaults to True.
         justify (str): `left`, `right` or `none`. Defaults to `left`. Says how
             the circuit should be justified.
-        idle_wires (bool): Include idle wires. Default is True.
+        idle_wires (bool): Include idle wires. Default is False.
         with_layout (bool): Include layout information, with labels on the physical
             layout. Default: True.
         fold (int): Number of vertical layers allowed before folding. Default is 25.

releasenotes/notes/closes_12361-d3ea2c442a4a74a7.yaml

@@ -0,0 +1,4 @@
+---
+upgrade_visualization:
+  - |
+    The default for the parameter ``idle_wires`` changed to ``False`` in all the circuit drawers. If you still want to see wires without instructions, set ``idle_wires=True`` explicitly. 

test/python/visualization/test_circuit_drawer.py

@@ -171,7 +171,9 @@ def test_wire_order(self):
                 "                  ",
             ]
         )
-        result = visualization.circuit_drawer(circuit, output="text", wire_order=[2, 3, 0, 1])
+        result = visualization.circuit_drawer(
+            circuit, output="text", idle_wires=True, wire_order=[2, 3, 0, 1]
+        )
         self.assertEqual(result.__str__(), expected)
 
     def test_wire_order_cregbundle(self):
@@ -205,7 +207,7 @@ def test_wire_order_cregbundle(self):
             ]
         )
         result = visualization.circuit_drawer(
-            circuit, output="text", wire_order=[2, 3, 0, 1], cregbundle=True
+            circuit, output="text", wire_order=[2, 3, 0, 1], cregbundle=True, idle_wires=True
         )
         self.assertEqual(result.__str__(), expected)
 
@@ -240,7 +242,9 @@ def test_reverse_bits(self):
                 "          ",
             ]
         )
-        result = visualization.circuit_drawer(circuit, output="text", reverse_bits=True)
+        result = visualization.circuit_drawer(
+            circuit, output="text", reverse_bits=True, idle_wires=True
+        )
         self.assertEqual(result.__str__(), expected)
 
     def test_warning_for_bad_justify_argument(self):
@@ -282,7 +286,7 @@ def test_no_explict_cregbundle(self):
                 "               ",
             ]
         )
-        result = circuit.draw("text")
+        result = circuit.draw("text", idle_wires=True)
         self.assertEqual(result.__str__(), expected)
         # Extra tests that no cregbundle (or any other) warning is raised with the default settings
         # for the other drawers, if they're available to test.

test/python/visualization/test_circuit_latex.py

@@ -53,7 +53,7 @@ def test_empty_circuit(self):
         """Test draw an empty circuit"""
         filename = self._get_resource_path("test_latex_empty.tex")
         circuit = QuantumCircuit(1)
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -76,8 +76,12 @@ def test_multi_underscore_reg_names(self):
         c_reg1 = ClassicalRegister(1, "c1_re_g__g")
         c_reg3 = ClassicalRegister(3, "c3_re_g__g")
         circuit = QuantumCircuit(q_reg1, q_reg3, c_reg1, c_reg3)
-        circuit_drawer(circuit, cregbundle=True, filename=filename1, output="latex_source")
-        circuit_drawer(circuit, cregbundle=False, filename=filename2, output="latex_source")
+        circuit_drawer(
+            circuit, cregbundle=True, filename=filename1, output="latex_source", idle_wires=True
+        )
+        circuit_drawer(
+            circuit, cregbundle=False, filename=filename2, output="latex_source", idle_wires=True
+        )
         self.assertEqualToReference(filename1)
         self.assertEqualToReference(filename2)
 
@@ -101,9 +105,9 @@ def test_4597(self):
         circuit = QuantumCircuit(qr, cr)
         with self.assertWarns(DeprecationWarning):
             circuit.x(qr[2]).c_if(cr, 2)
-        circuit.draw(output="latex_source", cregbundle=True)
+        circuit.draw(output="latex_source", cregbundle=True, idle_wires=True)
 
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -174,7 +178,7 @@ def test_no_ops(self):
         See https://github.com/Qiskit/qiskit-terra/issues/5393"""
         filename = self._get_resource_path("test_latex_no_ops.tex")
         circuit = QuantumCircuit(2, 3)
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -195,7 +199,7 @@ def test_long_name(self):
         circuit.h(qr)
         circuit.h(qr)
 
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, idle_wires=True, output="latex_source")
 
         self.assertEqualToReference(filename)
 
@@ -230,7 +234,7 @@ def test_plot_partial_barrier(self):
         circuit.barrier(0)
         circuit.h(q[0])
 
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -253,10 +257,14 @@ def test_plot_barriers(self):
         circuit.h(q[1])
 
         # check the barriers plot properly when plot_barriers= True
-        circuit_drawer(circuit, filename=filename1, output="latex_source", plot_barriers=True)
+        circuit_drawer(
+            circuit, filename=filename1, output="latex_source", plot_barriers=True, idle_wires=True
+        )
 
         self.assertEqualToReference(filename1)
-        circuit_drawer(circuit, filename=filename2, output="latex_source", plot_barriers=False)
+        circuit_drawer(
+            circuit, filename=filename2, output="latex_source", plot_barriers=False, idle_wires=True
+        )
 
         self.assertEqualToReference(filename2)
 
@@ -270,7 +278,7 @@ def test_no_barriers_false(self):
         circuit.h(q1[0])
         circuit.h(q1[1])
 
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, idle_wires=True, output="latex_source")
 
         self.assertEqualToReference(filename)
 
@@ -388,7 +396,12 @@ def test_creg_initial(self):
         circuit.x(1)
 
         circuit_drawer(
-            circuit, filename=filename1, output="latex_source", cregbundle=True, initial_state=True
+            circuit,
+            filename=filename1,
+            output="latex_source",
+            cregbundle=True,
+            initial_state=True,
+            idle_wires=True,
         )
 
         self.assertEqualToReference(filename1)
@@ -398,6 +411,7 @@ def test_creg_initial(self):
             output="latex_source",
             cregbundle=False,
             initial_state=False,
+            idle_wires=True,
         )
 
         self.assertEqualToReference(filename2)
@@ -503,7 +517,7 @@ def test_partial_layout(self):
             seed_transpiler=0,
         )
 
-        circuit_drawer(transpiled, filename=filename, output="latex_source")
+        circuit_drawer(transpiled, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -592,7 +606,7 @@ def test_inst_with_cbits(self):
         cr = ClassicalRegister(4, "cr")
         circuit = QuantumCircuit(qr, cr)
         circuit.append(inst, [qr[1], qr[2]], [cr[2], cr[1]])
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -633,7 +647,7 @@ def test_registerless_one_bit(self):
         qry = QuantumRegister(1, "qry")
         crx = ClassicalRegister(2, "crx")
         circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx)
-        circuit_drawer(circuit, filename=filename, output="latex_source")
+        circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True)
 
         self.assertEqualToReference(filename)
 
@@ -668,8 +682,12 @@ def test_measures_with_conditions_with_bits(self):
         with self.assertWarns(DeprecationWarning):
             circuit.x(0).c_if(crx[1], 0)
         circuit.measure(0, bits[3])
-        circuit_drawer(circuit, cregbundle=False, filename=filename1, output="latex_source")
-        circuit_drawer(circuit, cregbundle=True, filename=filename2, output="latex_source")
+        circuit_drawer(
+            circuit, cregbundle=False, filename=filename1, output="latex_source", idle_wires=True
+        )
+        circuit_drawer(
+            circuit, cregbundle=True, filename=filename2, output="latex_source", idle_wires=True
+        )
         self.assertEqualToReference(filename1)
         self.assertEqualToReference(filename2)
 
@@ -683,7 +701,12 @@ def test_conditions_with_bits_reverse(self):
         with self.assertWarns(DeprecationWarning):
             circuit.x(0).c_if(bits[3], 0)
         circuit_drawer(
-            circuit, cregbundle=False, reverse_bits=True, filename=filename, output="latex_source"
+            circuit,
+            cregbundle=False,
+            reverse_bits=True,
+            filename=filename,
+            output="latex_source",
+            idle_wires=True,
         )
         self.assertEqualToReference(filename)
 
@@ -695,7 +718,9 @@ def test_sidetext_with_condition(self):
         circuit = QuantumCircuit(qr, cr)
         with self.assertWarns(DeprecationWarning):
             circuit.append(CPhaseGate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1)
-        circuit_drawer(circuit, cregbundle=False, filename=filename, output="latex_source")
+        circuit_drawer(
+            circuit, cregbundle=False, filename=filename, output="latex_source", idle_wires=True
+        )
         self.assertEqualToReference(filename)
 
     def test_idle_wires_barrier(self):
@@ -725,6 +750,7 @@ def test_wire_order(self):
             wire_order=[2, 1, 3, 0, 6, 8, 9, 5, 4, 7],
             filename=filename,
             output="latex_source",
+            idle_wires=True,
         )
         self.assertEqualToReference(filename)