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Extracting design information via API #108

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svenka3 opened this issue Aug 4, 2022 · 0 comments

svenka3 commented Aug 4, 2022

I like the examples provided such as parser, dataflow etc. Thanks a lot for doing this great work!

Say I want to use PyVerilog to query design information such as:

ports
All net names
All escaped identifiers etc.

How do I approach? I looked at SignalAnalyze, visit_ports etc. but not clear on what the node argument and how to pass it. Any inputs please

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