Integration of AIA into openpiton

piton/design/chip/rtl/chip.v.pyv

@@ -156,6 +156,12 @@ module chip(
 `ifdef PITON_RV64_PLIC
     // PLIC
 ,   input   [`PITON_NUM_TILES*2-1:0]            irq_i           // level sensitive IR lines, mip & sip (async)
+`elsif  PITON_RV64_APLIC
+// APLIC
+`ifdef DIRECT_MODE
+,   input [`PITON_NUM_TILES-1:0][(`NR_DOMAINS*`NR_IDCs)-1:0]   irq_i                                    
+`endif // DIRECT_MODE
+
 `endif // ifdef PITON_RV64_PLIC
 `endif // ifdef PITON_RV64_PLATFORM
 );

piton/design/chip/tile/l15/rtl/l15_csm.v.pyv

@@ -402,15 +402,30 @@ end
 reg  on_chip_dev_access_s3;
 reg [`NOC_X_WIDTH-1:0] on_chip_dev_access_x_s3;
 reg [`NOC_Y_WIDTH-1:0] on_chip_dev_access_y_s3;
+reg aia_imsic_access_s3;
+reg [`HOME_ID_WIDTH-1:0] aia_imsic_access_flatid_s3;
+wire [`NOC_X_WIDTH-1:0] aia_imsic_access_x_s3;
+wire [`NOC_Y_WIDTH-1:0] aia_imsic_access_y_s3;
 always @ *
 begin
     //on-chip device accesses start with 0xE0 or 0xE1
     on_chip_dev_access_s3 = (l15_csm_req_address_s3[39:33] == 7'b1110000);
 
     on_chip_dev_access_x_s3 = l15_csm_req_address_s3[`ON_CHIP_DEV_X_POS];
     on_chip_dev_access_y_s3 = l15_csm_req_address_s3[`ON_CHIP_DEV_Y_POS];
+
+    // AIA IMSIC device accesses start with 0xE3
+    aia_imsic_access_s3 = (l15_csm_req_address_s3[39:32] == 8'he3);
+
+    aia_imsic_access_flatid_s3 = l15_csm_req_address_s3[`AIA_IMSIC_FLATID_POS];
 end
 
+flat_id_to_xy lhid_to_xy_imsic (
+    .flat_id(aia_imsic_access_flatid_s3[`HOME_ID_WIDTH-1:0]),
+    .x_coord(aia_imsic_access_x_s3),
+    .y_coord(aia_imsic_access_y_s3)
+    );
+
 `ifndef NO_RTL_CSM
 
 reg [`L15_HMC_ADDR_OP_WIDTH-1:0] addr_op_s3;
@@ -508,8 +523,21 @@ begin
         begin
             csm_l15_res_data_s3 = 0;
             csm_l15_res_data_s3[`PACKET_HOME_ID_CHIP_MASK] = 1'b0; // non-csm mode only has 1 chip alone
-            csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = on_chip_dev_access_s3 ? on_chip_dev_access_y_s3 : lhid_s3_y;
-            csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = on_chip_dev_access_s3 ? on_chip_dev_access_x_s3 : lhid_s3_x;
+            if (on_chip_dev_access_s3)
+            begin
+                csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = on_chip_dev_access_y_s3;
+                csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = on_chip_dev_access_x_s3;
+            end
+            else if (aia_imsic_access_s3)
+            begin
+                csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = aia_imsic_access_y_s3;
+                csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = aia_imsic_access_x_s3;
+            end
+            else
+            begin
+                csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = lhid_s3_y;
+                csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = lhid_s3_x;
+            end
         end
     end
 end
@@ -688,8 +716,21 @@ always @ *
 begin
     csm_l15_res_data_s3 = 0;
     csm_l15_res_data_s3[`PACKET_HOME_ID_CHIP_MASK] = 1'b0; // non-csm mode only has 1 chip alone
-    csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = on_chip_dev_access_s3 ? on_chip_dev_access_y_s3 : lhid_s3_y;
-    csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = on_chip_dev_access_s3 ? on_chip_dev_access_x_s3 : lhid_s3_x;
+    if (on_chip_dev_access_s3)
+    begin
+        csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = on_chip_dev_access_y_s3;
+        csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = on_chip_dev_access_x_s3;
+    end
+    else if (aia_imsic_access_s3)
+    begin
+        csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = aia_imsic_access_y_s3;
+        csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = aia_imsic_access_x_s3;
+    end
+    else
+    begin
+        csm_l15_res_data_s3[`PACKET_HOME_ID_Y_MASK] = lhid_s3_y;
+        csm_l15_res_data_s3[`PACKET_HOME_ID_X_MASK] = lhid_s3_x;
+    end
 end
 
 flat_id_to_xy lhid_to_xy (

piton/design/chip/tile/l15/rtl/noc1encoder.v

@@ -276,8 +276,18 @@ begin
    // Set fbits for on-chip device access according to the fbits field in addr
    // For interrupt controller access, hard code the fbits. This is DECADES_CHIP specific. 
    // otherwise set fbits to 0 (target L2)
-   msg_dest_fbits = (noc1buffer_noc1encoder_req_address[39:33] == 7'b1110000) ?
-                   noc1buffer_noc1encoder_req_address[`ON_CHIP_DEV_FBITS] : `NOC_FBITS_L2;
+   if (noc1buffer_noc1encoder_req_address[39:33] == 7'b1110000)
+   begin
+       msg_dest_fbits = noc1buffer_noc1encoder_req_address[`ON_CHIP_DEV_FBITS];
+   end
+   else if (noc1buffer_noc1encoder_req_address[39:32] == 8'he3)
+   begin
+       msg_dest_fbits = `NOC_FBITS_AIA;
+   end
+   else
+   begin
+       msg_dest_fbits = `NOC_FBITS_L2;
+   end
 
    // default value for a message, will be overwritten by interrupt reqs
    msg_dest_l2_xpos = req_dest_l2_xpos;