Adding support for Alveo U200/U250 to OpenPiton

.gitignore

@@ -78,6 +78,7 @@ piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
 !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
 !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
 !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
+*.bd
 
 # Ignore files generated for DMBR unit testing
 piton/verif/diag/assembly/princeton/dmbr_stream_hyper_gen.s

piton/design/chipset/include/mc_define.h

@@ -105,6 +105,25 @@
     `define DDR3_CS_WIDTH           2
     `define DDR3_BG_WIDTH           2
     `define DDR3_ODT_WIDTH          2
+`elsif ALVEO_BOARD
+    `define BOARD_MEM_SIZE_MB       16384
+    `define WORDS_PER_BURST         8
+    `define WORD_SIZE               8 // in bytes
+    `define MIG_APP_ADDR_WIDTH      32
+    `define MIG_APP_CMD_WIDTH       3
+    `define MIG_APP_DATA_WIDTH      512
+    `define MIG_APP_MASK_WIDTH      64
+
+    `define DDR3_DQ_WIDTH           72
+    `define DDR3_DQS_WIDTH          18
+    `define DDR3_ADDR_WIDTH         17
+    `define DDR3_BA_WIDTH           2
+    `define DDR3_DM_WIDTH           0
+    `define DDR3_CK_WIDTH           1
+    `define DDR3_CKE_WIDTH          1
+    `define DDR3_CS_WIDTH           1
+    `define DDR3_BG_WIDTH           2
+    `define DDR3_ODT_WIDTH          1    
 `elsif NEXYS4DDR_BOARD
     `define BOARD_MEM_SIZE_MB       256
     `define WORDS_PER_BURST         8

piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v

@@ -50,6 +50,7 @@ localparam SEND_HEADER = 2'd1;
 localparam SEND_DATA = 2'd2;
 
 reg [`AXI4_DATA_WIDTH-1:0] data_in_f;
+reg [`NOC_DATA_WIDTH-1:0] resp_header;
 
 wire in_go = in_val & in_rdy;
 wire flit_out_go = flit_out_val & flit_out_rdy;
@@ -118,7 +119,6 @@ always @(posedge clk) begin
   end
 end
 
-reg [`NOC_DATA_WIDTH-1:0] resp_header;
 always @(posedge clk) begin
   if (~rst_n) begin
     resp_header <= `NOC_DATA_WIDTH'b0;

piton/design/chipset/rtl/chipset.v

@@ -88,7 +88,16 @@ module chipset(
 
 `ifdef F1_BOARD
     input sys_clk,
-`else
+`elsif ALVEO_BOARD
+    input         pcie_refclk_clk_n    ,
+    input         pcie_refclk_clk_p    ,
+    input         pcie_perstn          ,		
+    input  [15:0] pci_express_x16_rxn  ,
+    input  [15:0] pci_express_x16_rxp  ,
+    output [15:0] pci_express_x16_txn  ,
+    output [15:0] pci_express_x16_txp  ,
+    input         resetn ,
+    output        chip_rstn ,
     // Oscillator clock
 `ifdef PITON_CHIPSET_CLKS_GEN
     `ifdef PITON_CHIPSET_DIFF_CLK
@@ -244,11 +253,11 @@ module chipset(
     output [`DDR3_CS_WIDTH-1:0]                 ddr_cs_n,
 `endif // endif NEXYSVIDEO_BOARD
 `ifdef PITONSYS_DDR4
-`ifdef XUPP3R_BOARD
+`ifdef PITONSYS_DDR4_PARITY
     output                                      ddr_parity,
 `else
     inout [`DDR3_DM_WIDTH-1:0]                  ddr_dm,
-`endif // XUPP3R_BOARD
+`endif // PITONSYS_DDR4_PARITY
 `else // PITONSYS_DDR4
     output [`DDR3_DM_WIDTH-1:0]                 ddr_dm,
 `endif // PITONSYS_DDR4
@@ -462,13 +471,13 @@ module chipset(
     `ifdef VCU118_BOARD
         // we only have 4 gpio dip switches on this board
         input  [3:0]                                        sw,
-    `elsif XUPP3R_BOARD
+    `elsif PITONSYS_NO_SWITCH
         // no switches :(
     `else         
         input  [7:0]                                        sw,
     `endif
 
-    `ifdef XUPP3R_BOARD
+    `ifdef PITONSYS_LED_4
      output [3:0]                                           leds
     `else 
      output [7:0]                                           leds
@@ -755,7 +764,7 @@ end
             `ifdef VCU118_BOARD
                 assign uart_boot_en    = sw[0];
                 assign uart_timeout_en = sw[1];
-            `elsif XUPP3R_BOARD
+            `elsif PITONSYS_NO_SWITCH
                 assign uart_boot_en    = 1'b1;
                 assign uart_timeout_en = 1'b0;
             `else 
@@ -813,6 +822,11 @@ end
     assign leds[1] = init_calib_complete;
     assign leds[2] = processor_offchip_noc2_valid;
     assign leds[3] = offchip_processor_noc3_valid;
+`elsif ALVEO_BOARD
+    assign leds[0] = 1'b1;
+    assign leds[1] = init_calib_complete;
+    assign leds[2] = processor_offchip_noc2_valid;
+    assign leds[3] = offchip_processor_noc3_valid;
 `else   // PITON_BOARD
     assign leds[0] = clk_locked;
     assign leds[1] = ~piton_ready_n;
@@ -1307,11 +1321,11 @@ chipset_impl_noc_power_test  chipset_impl (
                     .ddr_cs_n(ddr_cs_n),
                 `endif // endif NEXYSVIDEO_BOARD
 
-                `ifdef XUPP3R_BOARD
+                `ifdef PITONSYS_DDR4_PARITY
                     .ddr_parity(ddr_parity),
                 `else
                     .ddr_dm(ddr_dm),
-                `endif // XUPP3R_BOARD
+                `endif // PITONSYS_DDR4_PARITY
                 .ddr_odt(ddr_odt)
             `else // ifndef F1_BOARD
                 .mc_clk(mc_clk),
@@ -1420,6 +1434,20 @@ chipset_impl_noc_power_test  chipset_impl (
 
             `endif // PITON_FPGA_ETHERNETLITE   
     `endif // endif PITONSYS_IOCTRL
+
+    `ifdef ALVEO_BOARD
+        ,    // PCIe 
+        .pci_express_x16_rxn(pci_express_x16_rxn),
+        .pci_express_x16_rxp(pci_express_x16_rxp),
+        .pci_express_x16_txn(pci_express_x16_txn),
+        .pci_express_x16_txp(pci_express_x16_txp),
+        .pcie_perstn(pcie_perstn),
+        .pcie_refclk_clk_n(pcie_refclk_clk_n),
+        .pcie_refclk_clk_p(pcie_refclk_clk_p),
+        .resetn(resetn),
+        .chip_rstn (chip_rstn)
+
+    `endif
 
     `ifdef PITON_RV64_PLATFORM
     `ifdef PITON_RV64_DEBUGUNIT

piton/design/chipset/rtl/chipset_impl.v.pyv

@@ -87,6 +87,18 @@ module chipset_impl(
     // invalid access inside packet filter
     output                                      invalid_access_o,
 
+`ifdef ALVEO_BOARD
+    input         pcie_refclk_clk_n    ,
+    input         pcie_refclk_clk_p    ,
+    input         pcie_perstn          ,		
+    input  [15:0] pci_express_x16_rxn  ,
+    input  [15:0] pci_express_x16_rxp  ,
+    output [15:0] pci_express_x16_txn  ,
+    output [15:0] pci_express_x16_txp  ,
+    input         resetn ,
+    output        chip_rstn            ,
+`endif
+
 `ifndef PITONSYS_NO_MC
 `ifdef PITON_FPGA_MC_DDR3
 `ifndef F1_BOARD
@@ -152,11 +164,11 @@ module chipset_impl(
     output [`DDR3_CS_WIDTH-1:0]                 ddr_cs_n,
 `endif // endif NEXYSVIDEO_BOARD
 `ifdef PITONSYS_DDR4
-`ifdef XUPP3R_BOARD
+`ifdef PITONSYS_DDR4_PARITY
     output                                      ddr_parity,
 `else
     inout [`DDR3_DM_WIDTH-1:0]                  ddr_dm,
-`endif // XUPP3R_BOARD
+`endif // PITONSYS_DDR4_PARITY
 `else // PITONSYS_DDR4
     output [`DDR3_DM_WIDTH-1:0]                 ddr_dm,
 `endif // PITONSYS_DDR4
@@ -778,6 +790,55 @@ credit_to_valrdy noc3_xbar_to_%s(
             .m_axi_bready(m_axi_bready), 
             .ddr_ready(ddr_ready)
         );
+    `elsif ALVEO_BOARD
+        alveo_shell_top alveo_shell_i (
+
+            // PCIe 
+            .pci_express_x16_rxn(pci_express_x16_rxn),
+            .pci_express_x16_rxp(pci_express_x16_rxp),
+            .pci_express_x16_txn(pci_express_x16_txn),
+            .pci_express_x16_txp(pci_express_x16_txp),
+            .pcie_perstn(pcie_perstn),
+            .pcie_refclk_clk_n(pcie_refclk_clk_n),
+            .pcie_refclk_clk_p(pcie_refclk_clk_p),
+            .resetn(resetn),
+
+            // DDR4 physicall interface
+            .c0_ddr4_act_n             ( ddr_act_n                 ), // cas_n, ras_n and we_n are multiplexed in ddr4
+            .c0_ddr4_adr               ( ddr_addr                  ),
+            .c0_ddr4_ba                ( ddr_ba                    ),
+            .c0_ddr4_bg                ( ddr_bg                    ), // bank group address
+            .c0_ddr4_ck_t              ( ddr_ck_p                  ),
+            .c0_ddr4_ck_c              ( ddr_ck_n                  ),
+            .c0_ddr4_cke               ( ddr_cke                   ),
+            .c0_ddr4_cs_n              ( ddr_cs_n                  ),
+            .c0_ddr4_dq                ( ddr_dq                    ), 
+            .c0_ddr4_dqs_c             ( ddr_dqs_n                 ), 
+            .c0_ddr4_dqs_t             ( ddr_dqs_p                 ), 
+            .c0_ddr4_odt               ( ddr_odt                   ),
+            .c0_ddr4_par               ( ddr_parity                ),                        // output wire c0_ddr4_parity
+            .c0_ddr4_reset_n           ( ddr_reset_n               ),
+
+            // DDR4 clock & reset
+            .c0_sysclk_clk_p           ( mc_clk_p                 ),
+            .c0_sysclk_clk_n           ( mc_clk_n                 ),
+
+            .c0_init_calib_complete    ( init_calib_complete       ),
+
+            .chip_rstn                 (chip_rstn             ),
+            .chipset_clk               (chipset_clk           ),
+            .chipset_rstn              (chipset_rst_n          ),
+
+
+            .mem_flit_in_val(buf_mem_noc2_valid),
+            .mem_flit_in_data(buf_mem_noc2_data),
+            .mem_flit_in_rdy(mem_buf_noc2_ready),
+
+            .mem_flit_out_val(mem_buf_noc3_valid),
+            .mem_flit_out_data(mem_buf_noc3_data),
+            .mem_flit_out_rdy(buf_mem_noc3_ready)
+
+            );
     `else
         mc_top mc_top(
             .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst),
@@ -1121,7 +1182,7 @@ fake_uart fake_uart (
     // this is for selecting the right bootrom (1: baremetal, 0: linux)
     wire ariane_boot_sel;
 `ifdef PITON_FPGA_SYNTH
-  assign ariane_boot_sel   = uart_boot_en;
+    assign ariane_boot_sel   = uart_boot_en;
 `else
   `ifdef ARIANE_SIM_LINUX_BOOT
     assign ariane_boot_sel = 1'b0;

piton/design/chipset/xilinx/alveou200/.gitignore

@@ -0,0 +1,2 @@
+!ip_cores
+meep_shell