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Fix/io inits #438

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Fix/io inits #438

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e70db53
First try at making most audio I/O consistent at start
h4yn0nnym0u5e Jun 5, 2022
d49bdc9
Missed this one...
h4yn0nnym0u5e Jun 5, 2022
65641d7
Merge branch 'PaulStoffregen:master' into fix/io-inits
h4yn0nnym0u5e Jun 11, 2022
e7a9abf
Add setWire to keywords.txt
h4yn0nnym0u5e Jun 11, 2022
14bd6b2
Undo previous change
h4yn0nnym0u5e Jun 11, 2022
c1eeaca
Merge branch 'PaulStoffregen:master' into fix/io-inits
h4yn0nnym0u5e Dec 29, 2022
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6 changes: 4 additions & 2 deletions async_input_spdif3.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -96,14 +96,16 @@ void AsyncAudioInputSPDIF3::begin()
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.TCD->SADDR = (void *)((uint32_t)&SPDIF_SRL);
dma.TCD->DADDR = spdif_rx_buffer;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SPDIF_RX);

//SPDIF_SCR |=SPDIF_SCR_DMA_RX_EN; //DMA Receive Request Enable
dma.enable();
dma.attachInterrupt(isr);
dma.enable();

#ifdef DEBUG_SPDIF_IN
while (!Serial);
#endif

_bufferLPFilter.pCoeffs=new float[5];
_bufferLPFilter.numStages=1;
_bufferLPFilter.pState=new float[2];
Expand Down
36 changes: 19 additions & 17 deletions input_adc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -65,22 +65,6 @@ void AudioInputAnalog::init(uint8_t pin)
hpf_x1 = tmp; // With constant DC level x1 would be x0
hpf_y1 = 0; // Output will settle here when stable

// set the programmable delay block to trigger the ADC at 44.1 kHz
if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
|| PDB0_MOD != PDB_PERIOD
|| PDB0_IDLY != 1
|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
}
// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;

// set up a DMA channel to store the ADC data
dma.begin(true);
dma.TCD->SADDR = &ADC0_RA;
Expand All @@ -94,10 +78,28 @@ void AudioInputAnalog::init(uint8_t pin)
dma.TCD->DLASTSGA = -sizeof(analog_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(analog_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC0);

update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
dma.enable();

// set the programmable delay block to trigger the ADC at 44.1 kHz
if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
|| PDB0_MOD != PDB_PERIOD
|| PDB0_IDLY != 1
|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
}
// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
}


Expand Down
45 changes: 23 additions & 22 deletions input_adcs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -80,26 +80,6 @@ void AudioInputAnalogStereo::init(uint8_t pin0, uint8_t pin1)
hpf_x1[1] = tmp; // With constant DC level x1 would be x0
hpf_y1[1] = 0; // Output will settle here when stable


// set the programmable delay block to trigger the ADC at 44.1 kHz
//if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
//|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
//|| PDB0_MOD != PDB_PERIOD
//|| PDB0_IDLY != 1
//|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
PDB0_CH1C1 = 0x0101;
//}

// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
ADC1_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;

// set up a DMA channel to store the ADC data
dma0.begin(true);
dma1.begin(true);
Expand Down Expand Up @@ -133,11 +113,32 @@ void AudioInputAnalogStereo::init(uint8_t pin0, uint8_t pin1)
//dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC1);
dma1.triggerAtTransfersOf(dma0);
dma1.triggerAtCompletionOf(dma0);

update_responsibility = update_setup();
dma0.enable();
dma1.enable();
dma0.attachInterrupt(isr0);
dma1.attachInterrupt(isr1);
dma0.enable();
dma1.enable();

// set the programmable delay block to trigger the ADC at 44.1 kHz
//if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
//|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
//|| PDB0_MOD != PDB_PERIOD
//|| PDB0_IDLY != 1
//|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
PDB0_CH1C1 = 0x0101;
//}

// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
ADC1_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;

}


Expand Down
32 changes: 22 additions & 10 deletions input_i2s.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,13 @@ void AudioInputI2S::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX

Expand All @@ -81,13 +86,15 @@ void AudioInputI2S::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
#endif
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
dma.enable();

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
#endif
}

void AudioInputI2S::isr(void)
Expand Down Expand Up @@ -211,12 +218,13 @@ void AudioInputI2Sslave::begin(void)
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr);

#elif defined(__IMXRT1062__)
CORE_PIN8_CONFIG = 3; //1:RX_DATA0
Expand All @@ -233,13 +241,15 @@ void AudioInputI2Sslave::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S1_RCSR = 0;
I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
update_responsibility = update_setup();
dma.attachInterrupt(isr);
#endif
}

Expand Down Expand Up @@ -273,7 +283,9 @@ void AudioInputI2S::begin(void)
dma1.CFG->SAR = (void *)((uint32_t)&I2S0_RDR0 + 2);
dma1.CFG->DCR = (dma1.CFG->DCR & 0xF08E0FFF) | DMA_DCR_SSIZE(2);
dma1.destinationBuffer(i2s_rx_buffer1, sizeof(i2s_rx_buffer1));

dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);

dma1.interruptAtCompletion();
dma1.disableOnCompletion();
dma1.attachInterrupt(isr1);
Expand All @@ -283,14 +295,14 @@ void AudioInputI2S::begin(void)
dma2.destinationBuffer(i2s_rx_buffer2, sizeof(i2s_rx_buffer2));
dma2.interruptAtCompletion();
dma2.disableOnCompletion();
dma2.attachInterrupt(isr2);

update_responsibility = update_setup();
dma2.attachInterrupt(isr2); // isr2 triggers update_all()
dma1.enable();

I2S0_RCSR = 0;
I2S0_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FWDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX

update_responsibility = update_setup();
dma1.enable();
}

void AudioInputI2S::update(void)
Expand Down
15 changes: 8 additions & 7 deletions input_i2s2.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -62,14 +62,15 @@ void AudioInputI2S2::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s2_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S2_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; // page 2099
I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // page 2087

update_responsibility = update_setup();
dma.attachInterrupt(isr);
}

void AudioInputI2S2::isr(void)
Expand Down Expand Up @@ -195,14 +196,14 @@ void AudioInputI2S2slave::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s2_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);
dma.enable();

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S2_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; // page 2099
I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // page 2087
update_responsibility = update_setup();
dma.attachInterrupt(isr);

}
#endif
8 changes: 5 additions & 3 deletions input_i2s_hex.cpp
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Expand Up @@ -79,14 +79,16 @@ void AudioInputI2SHex::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

//I2S1_RCSR = 0;
//I2S1_RCR3 = I2S_RCR3_RCE_2CH << pinoffset;
I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
}

void AudioInputI2SHex::isr(void)
Expand Down
6 changes: 4 additions & 2 deletions input_i2s_oct.cpp
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Expand Up @@ -71,12 +71,14 @@ void AudioInputI2SOct::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
dma.enable();

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
}

void AudioInputI2SOct::isr(void)
Expand Down
12 changes: 7 additions & 5 deletions input_i2s_quad.cpp
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Expand Up @@ -69,12 +69,13 @@ void AudioInputI2SQuad::begin(void)
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
#endif
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr);

#elif defined(__IMXRT1062__)
const int pinoffset = 0; // TODO: make this configurable...
Expand Down Expand Up @@ -113,15 +114,16 @@ void AudioInputI2SQuad::begin(void)
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S1_RCSR = 0;
I2S1_RCR3 = I2S_RCR3_RCE_2CH << pinoffset;

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
#endif
}

Expand Down
6 changes: 3 additions & 3 deletions input_pdm.cpp
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Expand Up @@ -139,13 +139,12 @@ void AudioInputPDM::begin()
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
//I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
//I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX

dma.attachInterrupt(isr);
}


Expand Down Expand Up @@ -261,12 +260,13 @@ void AudioInputPDM::begin(void)
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr);
}
#endif

Expand Down
4 changes: 2 additions & 2 deletions input_pdm_i2s2.cpp
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Expand Up @@ -131,12 +131,12 @@ void AudioInputPDM2::begin(void)
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();

I2S2_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;

dma.attachInterrupt(isr);
}

extern const int16_t enormous_pdm_filter_table[];
Expand Down
1 change: 1 addition & 0 deletions input_spdif3.cpp
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Expand Up @@ -63,6 +63,7 @@ void AudioInputSPDIF3::begin(void)
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SPDIF_RX);

update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();
Expand Down
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