3.0

See Changelog for more details

What's Changed

• Improve performance of RAW FRAMED mode by @thomascobb in #5
• Allow building for multiple platforms (zynq and zynqmp) by @EmilioPeJu in #10
• Start using new toolchain by @EmilioPeJu in #11
• added PCAP ARM timestamp by @valerixb in #12
• Extension helper by @Araneidae in #15
• Remove !nm from simserver target by @MichaelStubbings in #19
• Update zpkg filename by @MichaelStubbings in #18
• add new register FPGA_CAPABILITIES to match PandABlocks-FPGA by @shu-soleil in #27
• Changes to CI to run within container by @tomtrafford in #32
• Get start timestamp and add it to header by @EmilioPeJu in #34
• Changes for compatibility with Vivado2022.2 kernel by @glennchid in #35
• Use a reasonable size of the backlog for the extension server socket by @EmilioPeJu in #36
• Don't advance capture ring buffer in response to new START interrupt by @Araneidae in #38
• Change ext_out samples from unscaled to scaled by @Araneidae in #41
• Use new *REG.NOMINAL_CLOCK register to define clock frequency by @Araneidae in #42

Full Changelog: 2.0.2...3.0