Autogenerate assembler functions for bit_bus and pos_bus

[glennchid]

The ordering of signals on the bit_bus and pos_bus for the fixed blocks are determined by the ordering of the blocks and fields within the blocks in the ini files, and the signals assignment is currently hard-coded in the top-level HDL file using concatentiton, and must match the ordering from the ini files. eg

bit_bus(BIT_BUS_SIZE-1 downto 0 ) <= pcap_active & outenc_clk & inenc_conn &
                                   inenc_data & inenc_z & inenc_b & inenc_a &
                                   lvdsin_val & ttlin_val;

pos_bus(POS_BUS_SIZE-1 downto 0) <= inenc_val;

A better approach is to autogenerate assembler functions for each target which specify the bit-fields within the bit-bus. addr_defines.vhd seems like the obvious place for this. Python/jinja would then fill in the signal names for the buses and the relevant indices (which are already calculated eg for registers to produce something like the following:

    function assemble_bitbus(ttlin_val, lvdsin_val, inenc_a, inenc_b, inenc_z, inenc_data, inenc_conn, outenc_clk, pcap_active : std_logic_vector)
        return std_logic_vector;

    function assemble_posbus(inenc_val : std32_array)
        return std32_array;

end addr_defines;

package body addr_defines is

    function assemble_bitbus(ttlin_val, lvdsin_val, inenc_a, inenc_b, inenc_z, inenc_data, inenc_conn, outenc_clk, pcap_active: std_logic_vector)
            return std_logic_vector is
        variable result : std_logic_vector(BIT_BUS_SIZE-1 downto 0);
    begin
        result(5 downto 0) := ttlin_val;
        result(7 downto 6) := lvdsin_val;
        result(11 downto 8) := inenc_a;
        result(15 downto 12) := inenc_b;
        result(19 downto 16) := inenc_z;
        result(23 downto 20) := inenc_data;
        result(27 downto 24) := inenc_conn;
        result(31 downto 28) := outenc_clk;
        result(32) := pcap_active(0);
        return result;
    end;

    function assemble_posbus(inenc_val : std32_array)
            return std32_array is
        variable result : std32_array(POS_BUS_SIZE-1 downto 0);
    begin
        result(3 downto 0) := inenc_val;
        return result;
    end;

end addr_defines;

This can be called as follows:

bit_bus(BIT_BUS_SIZE-1 downto 0) <= assemble_bitbus(ttlin_val => ttlin_val,
                                                    lvdsin_val => lvdsin_val,
                                                    inenc_a => inenc_a,
                                                    inenc_b => inenc_b,
                                                    inenc_z => inenc_z,
                                                    inenc_data => inenc_data,
                                                    inenc_conn => inenc_conn,
                                                    outenc_clk => outenc_clk,
                                                    pcap_active => pcap_active);

pos_bus(POS_BUS_SIZE-1 downto 0) <= assemble_posbus(inenc_val => inenc_val);

[Araneidae]

It might be slightly cleaner to generate assemble_bitbus as:

function assemble_bitbus(ttlin_val, lvdsin_val, inenc_a, inenc_b, inenc_z, inenc_data, inenc_conn, outenc_clk, pcap_active: std_logic_vector)
            return std_logic_vector is
begin
    return (
        5 downto 0 => ttlin_val,
        7 downto 6 => lvdsin_val,
        11 downto 8 => inenc_a,
        15 downto 12 => inenc_b,
        19 downto 16 => inenc_z,
        23 downto 20 => inenc_data,
        27 downto 24 => inenc_conn,
        31 downto 28 => outenc_clk,
        32 downto 32 => pcap_active,
        127 downto 33 => (others => '0')
    );
end;

[glennchid]

Thanks, yes the aggregate assignment is neater, but we have to be careful not to assign to more than BIT_BUS_SIZE (eg 32 in this case) as the rest will be assigned elsewhere.