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Multiple bug fixes to run parsec benchmark #189

Merged
merged 5 commits into from
Oct 17, 2024
Merged

Multiple bug fixes to run parsec benchmark #189

merged 5 commits into from
Oct 17, 2024

Commits on Oct 16, 2024

  1. cpu: Fix difftest skipping lr.aq 

    Change-Id: Ied973af5919b83c9fb88b66763958bbde11981d8
    @notlqr
    notlqr committed Oct 16, 2024
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  2. cpu-o3: Difftest: Add more CSRs and amo PageFault 

    Change-Id: I986028fc43759dfa5d9c486687e971e931a730cb
    @notlqr
    notlqr committed Oct 16, 2024
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  3. cpu-o3: Add store misaligned exception 

    Change-Id: Icfa64a99b9af5cb8fba58b45ce6712df46f2c012
    @notlqr
    notlqr committed Oct 16, 2024
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  4. cpu-o3: Let issue q automatially skip issue if not bypassed 

    No need to signal from L1D now

Change-Id: I20db1f49e254adb518a8150b6c091358d21d2310
    @notlqr
    notlqr committed Oct 16, 2024
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  5. cpu-o3: Fix tlb priv race when handling trap 

    Previously, `fault->invoke()` updates priv immediately, TLB also
translate using new priv. There still might be some instructions going
to IEW at the moment. This is because interrupt traps when ROB is empty,
but somehow these instructions are not in ROB yet.
Such data race on processor PRIV causes mem accesses to bypass addr
translation, thereby accessing a non-existent paddr, which would not be
filtered out because GEM5 thinks they are PIO addrs.
This fix makes TLB use old privilege mode until squashing signal is
sent to IEW.

Change-Id: I016e81069d090269afe4e40f14396cd9163f9ccd
    @notlqr
    notlqr committed Oct 16, 2024
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