Changing fuPool in XiangshanCore has no impact on the simulation results

[DCliuzhe]

I have replaced the fuPool in XiangshanCore with my own defined one(Actually with some changes in num of the units). But there is no difference in simulation results before and after the change. May I ask what is the reason?

[shinezyy]

Can you provide config.ini file produced from both simulations ( before and after modifications)?

[DCliuzhe]

Here they are.
origin.txt
change.txt

[tastynoob]

Actually, the fupool has been deprecated in xs-gem5, please see FUPool.py scheduler

[shinezyy]

@DCliuzhe Can you also provide

1. how you modify the code of xs-gem5? For example, Screenshot or log of git diff src
2. the workload you are using and how you compile the workload

[DCliuzhe]

Of course. Actually, my change is simple:

index f0f2d70772..73c5dc036f 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -130,7 +130,7 @@ class SIMD_Unit(FUDesc):
                OpDesc(opClass='VectorMisc'),
                OpDesc(opClass='VectorIntegerExtension'),
                OpDesc(opClass='VectorConfig')]
-    count = 2
+    count = 3
 
 class PredALU(FUDesc):
     opList = [ OpDesc(opClass='SimdPredAlu') ]```

[DCliuzhe]

My workload was compiled by using AM. The workload is a GEMM implemented in RVV.

[eastonman]

I suppose your change just modifies the default number of Fu.
FUPOOL is no longer used in the current version of xs-gem5.
FYI I am recently modeling an Apple-M4-like core at ecc9849
Hopefully this is helpful to you.

[DCliuzhe]

Thank you for the code you provided. However, I followed your approach and modified the scheduler in src/cpu/FuPool.py as follows, but the number of cycles obtained by simulation did not change.

index f301815de7..8836acfb9a 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -172,7 +172,7 @@ class KunminghuScheduler(Scheduler):
         IssueQue(name='IQ_stu', inoutPorts=2, size=2*24, fuType=[WritePort()]),
         IssueQue(name='IQ_ldu', inoutPorts=2, size=2*24, fuType=[ReadPort()]),
         IssueQue(name='IQ_cplx',inoutPorts=2, size=2*24,
-            scheduleToExecDelay=3, fuType=[FP_MISC(), FP_SLOW(), FP_MAM(), FP_MAA(), SIMD_Unit()])
+            scheduleToExecDelay=3, fuType=[FP_MISC(), FP_SLOW(), FP_MAM(), FP_MAA(), SIMD_Unit(count = 4)])
     ]
     slotNum = 12
     xbarWakeup = True