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arch-riscv: clean H-MMU code
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Change-Id: I19711d3828c257abcd084f2bacc04f1d58031753
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@jueshiwenli
jueshiwenli committed Sep 14, 2024
1 parent d910923 commit eb02c8a
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Showing 13 changed files with 149 additions and 269 deletions.
11 changes: 6 additions & 5 deletions src/arch/riscv/faults.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -168,16 +168,17 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
((v) && ((0 <= _code && _code <= 7 && _code != 2) || _code == INST_PAGE ||
_code == LOAD_PAGE || _code == STORE_PAGE)));
hstatus.spv = v;
if (v)
if (v) {
hstatus.spvp = pp;
}
if (_code == INST_PAGE || _code == LOAD_PAGE || _code == STORE_PAGE ||
_code == LOAD_ADDR_MISALIGNED || _code == STORE_ADDR_MISALIGNED || _code == INST_ACCESS ||
_code == LOAD_ACCESS || _code == STORE_ACCESS)
_code == LOAD_ACCESS || _code == STORE_ACCESS) {
tc->setMiscReg(MISCREG_HTVAL, 0);
else if ((_code != INSTG_PAGE) && (_code != LOADG_PAGE) && (_code != STOREG_PAGE))
}
else if ((_code != INSTG_PAGE) && (_code != LOADG_PAGE) && (_code != STOREG_PAGE)) {
tc->setMiscReg(MISCREG_HTVAL, 0);


}
tc->setMiscReg(MISCREG_VIRMODE, 0);
}
break;
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13 changes: 4 additions & 9 deletions src/arch/riscv/isa.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -318,10 +318,7 @@ void ISA::clear()
std::fill(miscRegFile.begin(), miscRegFile.end(), 0);

miscRegFile[MISCREG_PRV] = PRV_M;
//miscRegFile[MISCREG_ISA] = 0x800000000034112f;
miscRegFile[MISCREG_ISA] = 0x80000000003411af;
//miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x34112D;
//miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x1411ad;
miscRegFile[MISCREG_VENDORID] = 0;
miscRegFile[MISCREG_ARCHID] = 0;
miscRegFile[MISCREG_IMPID] = 0;
Expand All @@ -334,7 +331,6 @@ void ISA::clear()
(1ULL << FS_OFFSET);
}
miscRegFile[MISCREG_MCOUNTEREN] = 0x0;
// miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
miscRegFile[MISCREG_SCOUNTEREN] = 0;
// don't set it to zero; software may try to determine the supported
// triggers, starting at zero. simply set a different value here.
Expand All @@ -343,7 +339,6 @@ void ISA::clear()
miscRegFile[MISCREG_NMIE] = 1;

miscRegFile[MISCREG_VTYPE] = (1lu<<63);
//(HSTATUS) reg_num.vsxl =2;
miscRegFile[MISCREG_HSTATUS] = (uint64_t)2<<32;
miscRegFile[MISCREG_VSSTATUS] = miscRegFile[MISCREG_STATUS] & NEMU_SSTATUS_RMASK;
miscRegFile[MISCREG_ARCHID] = 0x19;
Expand Down Expand Up @@ -409,16 +404,16 @@ ISA::readMiscReg(int misc_reg)
if ((v == 1) && (misc_reg == MISCREG_SATP)) {
return readMiscRegNoEffect(MISCREG_VSATP);
}
if ((v == 1) && (misc_reg == MISCREG_SEPC)){
if ((v == 1) && (misc_reg == MISCREG_SEPC)) {
return readMiscRegNoEffect(MISCREG_VSEPC);
}
if ((v == 1) && (misc_reg == MISCREG_STVAL)){
if ((v == 1) && (misc_reg == MISCREG_STVAL)) {
return readMiscRegNoEffect(MISCREG_VSTVAL);
}
if ((v == 1) && (misc_reg == MISCREG_SCAUSE)){
if ((v == 1) && (misc_reg == MISCREG_SCAUSE)) {
return readMiscRegNoEffect(MISCREG_VSCAUSE);
}
if ((v == 1) && (misc_reg == MISCREG_STVEC)){
if ((v == 1) && (misc_reg == MISCREG_STVEC)) {
return readMiscRegNoEffect(MISCREG_VSTVEC);
}
if (misc_reg == MISCREG_HIE) {
Expand Down
6 changes: 3 additions & 3 deletions src/arch/riscv/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -4330,14 +4330,14 @@ decode QUADRANT default Unknown::unknown() {
auto hstatus_spv = hstatus.spv;
auto pm = (PrivilegeMode)xc->readMiscReg(
MISCREG_PRV);
bool writeSign = false;
bool write_sign = false;
if(v ==0){
hstatus.spv =0;
xc->setMiscReg(MISCREG_HSTATUS, hstatus);

}
else{
writeSign = true;
write_sign = true;
if((pm == PRV_S && hstatus.vtsr) || pm < PRV_S){
panic("todo EX_VI");
}
Expand All @@ -4358,7 +4358,7 @@ decode QUADRANT default Unknown::unknown() {
}
NPC = xc->readMiscReg(MISCREG_VSEPC);
}
if(!writeSign){
if(!write_sign){
if (pm == PRV_U ||
(pm == PRV_S && status.tsr == 1)) {
return std::make_shared<IllegalInstFault>(
Expand Down
5 changes: 3 additions & 2 deletions src/arch/riscv/isa/formats/standard.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -345,8 +345,9 @@ def template CSRExecute {{
RegVal data, olddata;
auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if ((pm < lowestAllowedMode)&&
((csr <CSR_HSTATUS) ||(csr >CSR_HGATP)) && ((csr <CSR_VSSTATUS) ||(csr > CSR_VSATP))) {
if ((pm < lowestAllowedMode) && ((csr <CSR_HSTATUS
) ||(csr >CSR_HGATP)) && ((csr <CSR_VSSTATUS) || (
csr > CSR_VSATP))) {
return std::make_shared<IllegalInstFault>(
csprintf("%s is not accessible in %s\n", csrName, pm),
machInst);
Expand Down
2 changes: 2 additions & 0 deletions src/arch/riscv/pagetable.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,8 @@ const Addr TWO_STAGE_L2_LEVEL_MASK = 0x7ff;
const Addr VPN_MASK = 0x1ff;
const Addr PGSHFT = 12;
const Addr PTESIZE = 8;
const Addr L2PageTypeNum = 4;
const Addr L2PageStoreTypeNum = 5;

const Addr L2TLB_BLK_OFFSET = 3;
const Addr VADDR_CHOOSE_MASK = 7;
Expand Down
78 changes: 40 additions & 38 deletions src/arch/riscv/pagetable_walker.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -267,8 +267,7 @@ void
Walker::WalkerState::initState(ThreadContext *_tc, const RequestPtr &_req, BaseMMU::Mode _mode, bool _isTiming,
bool _from_forward_pre_req, bool _from_back_pre_req)
{
if (_req == nullptr)
assert(0);
assert(_req != nullptr);
if (_req->get_two_stage_state()) {
assert(state == Ready);
started = false;
Expand Down Expand Up @@ -602,8 +601,9 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
if (pte.v && !pte.r && !pte.w && !pte.x) {
twoStageLevel--;
if (twoStageLevel < 0) {
doEndWalk = true;
assert(0);
endWalk();
warn("pagefault in Gstage ptw twostagelevel <0\n");
return endGstageWalk();
} else {
nextRead = (pte.ppn << PageShift) + (getGVPNi(gPaddr, twoStageLevel) * PTESIZE);
nextcheck = nextRead;
Expand Down Expand Up @@ -638,19 +638,16 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)

} else if (!pte.v || (!pte.r && pte.w)) {
endWalk();
GstageFault = true;
fault = pageFault(true, true);
return fault;
return endGstageWalk();
} else if (!pte.u) {
doEndWalk = true;
assert(0);
} else if (((mode == BaseMMU::Execute) || (isHInst)) && (!pte.x)) {
doEndWalk = true;
assert(0);
endWalk();
return endGstageWalk();
} else if (((mode == BaseMMU::Execute) || isHInst) && (!pte.x)) {
endWalk();
return endGstageWalk();
} else if ((mode == BaseMMU::Read) && (!pte.r && !(status.mxr && pte.x))) {
doEndWalk = true;
assert(0);

endWalk();
return endGstageWalk();
} else if ((mode == BaseMMU::Write) && !(pte.r && pte.w)) {
endWalk();
GstageFault = true;
Expand Down Expand Up @@ -708,19 +705,22 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
gstage);
}

else if (l2_level == 1) // hit level =1
else if (l2_level == 1) {
walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2sp2, l2_i, false,
gstage);
else if (l2_level == 2) //
} // hit level =1

else if (l2_level == 2) {
walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2sp1, l2_i, false,
gstage);
}
}
}
}

if ((gPaddr & ~(((int64_t)1 << 41) - 1)) != 0) {
// this is a excep
assert(0);
panic("address fault\n");
}
DPRINTF(PageTableWalkerTwoStage, "twoStageStepWalk gpaddr %lx vaddr %lx\n", gPaddr, entry.vaddr);
gpaddrMode =1;
Expand All @@ -732,10 +732,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
entry.paddr = gPaddr >> 12;
entry.pte = pte;
int put_level = 0;
if (twoStageLevel < level)
put_level = twoStageLevel;
else
put_level = level;
put_level = std::min(twoStageLevel, level);

entry.logBytes = PageShift + (put_level * LEVEL_BITS);
entry.level = put_level;
Expand Down Expand Up @@ -763,7 +760,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
bool tlb_hit = false;

if (walker->l2tlb == nullptr)
assert(0);
panic("walker->l2tlb is none\n");
if (inGstage) {
for (int i_e = 1; i_e < 6; i_e++) {
e[i_e] = walker->l2tlb->lookupL2TLB(nextcheck, hgatp.vmid, mode, false, i_e, true, gstage);
Expand All @@ -772,7 +769,6 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
e[0] = e[i_e];
hit_level = e[i_e]->level;
}
// assert(0);
}
if (e[0] && (twoStageLevel == e[0]->level)) {
tlbHit = true;
Expand Down Expand Up @@ -819,10 +815,10 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
DPRINTF(PageTableWalker, "Loading level%d PTE from %#x vaddr %#x\n", level, nextRead, entry.vaddr);
}
} else {
assert(0);
panic("wrong in G ptw\n");
}
} else {
assert(0);
panic("wrong in G ptw\n");
}

return fault;
Expand Down Expand Up @@ -1082,7 +1078,7 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write)
}
}
} else {
assert(0);
panic("wrong in G ptw\n");
}

return fault;
Expand Down Expand Up @@ -1455,6 +1451,13 @@ Walker::WalkerState::endWalk()
read = NULL;
}
Fault
Walker::WalkerState::endGstageWalk()
{
endWalk();
GstageFault = true;
return pageFault(true, true);
}
Fault
Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr)
{
Addr PgBase = ppn << 12;
Expand All @@ -1469,7 +1472,7 @@ Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr)
warn("missaligned superpage vaddr %lx\n", entry.vaddr);
fault = pageFault(true, false);
endWalk();
assert(0);
panic("address check wrong in from tlb ptw\n");
return fault;
}
PgBase = (PgBase & ~pg_mask) | (gPaddr & pg_mask & ~PGMASK);
Expand All @@ -1480,7 +1483,7 @@ Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr)
gPaddr = nextRead;
if ((gPaddr & ~(((int64_t)1 << 41) - 1)) != 0) {
// this is a excep
assert(0);
panic("address check wrong in from tlb ptw\n");
}
DPRINTF(PageTableWalkerTwoStage, "twoStageStepWalk gpaddr %lx vaddr %lx\n", gPaddr, entry.vaddr);
gpaddrMode = 1;
Expand Down Expand Up @@ -1524,7 +1527,7 @@ Walker::WalkerState::startTwoStageWalk(Addr ppn, Addr vaddr)
Addr TwoLevelTopAddr = 0;
if ((ppn & ~(((int64_t)1 << 41) - 1)) != 0) {
// this is a excep
assert(0);
panic("address check wrong in start ptw\n");
}
TwoLevelTopAddr = (hgatp.ppn << PageShift) + (idx * sizeof(PTESv39));

Expand All @@ -1540,7 +1543,7 @@ Walker::WalkerState::startTwoStageWalk(Addr ppn, Addr vaddr)
read->allocate();

} else {
assert(0);
panic("hgatp.mode != 8 \n");
}
return NoFault;
}
Expand Down Expand Up @@ -1734,13 +1737,11 @@ Walker::WalkerState::recvPacket(PacketPtr pkt)
nextState = Ready;
PacketPtr write = NULL;
read = pkt;
if ((translateMode == twoStageMode) && (inGstage)){
if ((translateMode == twoStageMode) && (inGstage)) {
mainFault = twoStageStepWalk(write);
}
else if ((translateMode == twoStageMode) && (!inGstage)){
} else if ((translateMode == twoStageMode) && (!inGstage)) {
mainFault = twoStageWalk(write);
}
else{
} else {
mainFault = stepWalk(write);
}
state = Waiting;
Expand Down Expand Up @@ -1779,7 +1780,7 @@ Walker::WalkerState::recvPacket(PacketPtr pkt)
if (mainFault != NoFault) {
warn("paddr overflow vaddr: %lx paddr: lx\n", vaddr, paddr);
r.translation->finish(mainFault, r.req, r.tc, mode);
assert(0);
panic("paddr overflow\n");
return false;
}
r.translation->finish(mainFault, r.req, r.tc, mode);
Expand Down Expand Up @@ -2015,8 +2016,9 @@ Walker::WalkerState::pageFaultOnRequestor(RequestorState &r, bool G)
if (r.req->isInstFetch()) {
if (r.req->getPC() < page_start) {
vaddr = page_start;
} else
} else {
vaddr = r.req->getPC();
}

} else {
vaddr = r.req->getVaddr();
Expand Down
1 change: 1 addition & 0 deletions src/arch/riscv/pagetable_walker.hh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -246,6 +246,7 @@ namespace RiscvISA
Fault stepWalk(PacketPtr &write);
void sendPackets();
void endWalk();
Fault endGstageWalk();
Fault pageFault(bool present, bool G);
Fault pageFaultOnRequestor(RequestorState &requestor, bool G);
Addr getGVPNi(Addr vaddr, int level);
Expand Down
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