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cpu-o3: Fix tlb priv race when handling trap
Previously, `fault->invoke()` updates priv immediately, TLB also translate using new priv. There still might be some instructions going to IEW at the moment. This is because interrupt traps when ROB is empty, but somehow these instructions are not in ROB yet. Such data race on processor PRIV causes mem accesses to bypass addr translation, thereby accessing a non-existent paddr, which would not be filtered out because GEM5 thinks they are PIO addrs. This fix makes TLB use old privilege mode until squashing signal is sent to IEW. Change-Id: I016e81069d090269afe4e40f14396cd9163f9ccd
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