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Merge pull request #15 from felipebalbi/espi-per-port-bits
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espi: split port interrupt bits
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@felipebalbi
felipebalbi authored Feb 3, 2025
2 parents b18c178 + cf8f4f5 commit c8d21d2
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Showing 6 changed files with 311 additions and 41 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "mimxrt633s-pac"
version = "0.1.0"
version = "0.2.0"
authors = [ "Felipe Balbi <[email protected]>" ]
edition = "2021"
license = "MIT"
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25 changes: 24 additions & 1 deletion patch/espi.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -108,8 +108,8 @@ ESPI:
_array:
PENA*: {}

# Mark W1C bits accordingly
MSTAT:
# Mark W1C bits accordingly
_modify:
P80Int:
modifiedWriteValues: oneToClear
Expand All @@ -128,3 +128,26 @@ ESPI:

GPIO:
modifiedWriteValues: oneToClear

# Split PortInt bits
_split:
PortInt:
name: PORT_INT%s

INTENSET:
# Split PortInt bits
_split:
PortInt:
name: PORT_INT%s

INTENCLR:
# Split PortInt bits
_split:
PortInt:
name: PORT_INT%s

INTSTAT:
# Split PortInt bits
_split:
PortInt:
name: PORT_INT%s
82 changes: 71 additions & 11 deletions src/espi/intenclr.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,26 @@
pub type R = crate::R<IntenclrSpec>;
#[doc = "Register `INTENCLR` writer"]
pub type W = crate::W<IntenclrSpec>;
#[doc = "Field `PortInt` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortIntR = crate::FieldReader;
#[doc = "Field `PortInt` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `PORT_INT0` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt0R = crate::BitReader;
#[doc = "Field `PORT_INT0` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT1` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt1R = crate::BitReader;
#[doc = "Field `PORT_INT1` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT2` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt2R = crate::BitReader;
#[doc = "Field `PORT_INT2` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT3` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt3R = crate::BitReader;
#[doc = "Field `PORT_INT3` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT4` reader - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt4R = crate::BitReader;
#[doc = "Field `PORT_INT4` writer - If set to 1, clears corresponding port interrupt enable"]
pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P80Int` reader - If set to 1, clears Port80 interrupt enable."]
pub type P80intR = crate::BitReader;
#[doc = "Field `P80Int` writer - If set to 1, clears Port80 interrupt enable."]
Expand Down Expand Up @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader;
#[doc = "Field `GPIO` writer - If set to 1, clears GPIO interrupt enable."]
pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - If set to 1, clears corresponding port interrupt enable"]
#[doc = "Bit 0 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int(&self) -> PortIntR {
PortIntR::new((self.bits & 0x1f) as u8)
pub fn port_int0(&self) -> PortInt0R {
PortInt0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int1(&self) -> PortInt1R {
PortInt1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int2(&self) -> PortInt2R {
PortInt2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int3(&self) -> PortInt3R {
PortInt3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int4(&self) -> PortInt4R {
PortInt4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 8 - If set to 1, clears Port80 interrupt enable."]
#[inline(always)]
Expand Down Expand Up @@ -80,22 +116,46 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTENCLR")
.field("port_int", &self.port_int())
.field("p80int", &self.p80int())
.field("bus_rst", &self.bus_rst())
.field("irq_upd", &self.irq_upd())
.field("wire_chg", &self.wire_chg())
.field("hstall", &self.hstall())
.field("crcerr", &self.crcerr())
.field("gpio", &self.gpio())
.field("port_int0", &self.port_int0())
.field("port_int1", &self.port_int1())
.field("port_int2", &self.port_int2())
.field("port_int3", &self.port_int3())
.field("port_int4", &self.port_int4())
.finish()
}
}
impl W {
#[doc = "Bits 0:4 - If set to 1, clears corresponding port interrupt enable"]
#[doc = "Bit 0 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int0(&mut self) -> PortInt0W<IntenclrSpec> {
PortInt0W::new(self, 0)
}
#[doc = "Bit 1 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int1(&mut self) -> PortInt1W<IntenclrSpec> {
PortInt1W::new(self, 1)
}
#[doc = "Bit 2 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int2(&mut self) -> PortInt2W<IntenclrSpec> {
PortInt2W::new(self, 2)
}
#[doc = "Bit 3 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int3(&mut self) -> PortInt3W<IntenclrSpec> {
PortInt3W::new(self, 3)
}
#[doc = "Bit 4 - If set to 1, clears corresponding port interrupt enable"]
#[inline(always)]
pub fn port_int(&mut self) -> PortIntW<IntenclrSpec> {
PortIntW::new(self, 0)
pub fn port_int4(&mut self) -> PortInt4W<IntenclrSpec> {
PortInt4W::new(self, 4)
}
#[doc = "Bit 8 - If set to 1, clears Port80 interrupt enable."]
#[inline(always)]
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82 changes: 71 additions & 11 deletions src/espi/intenset.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,26 @@
pub type R = crate::R<IntensetSpec>;
#[doc = "Register `INTENSET` writer"]
pub type W = crate::W<IntensetSpec>;
#[doc = "Field `PortInt` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortIntR = crate::FieldReader;
#[doc = "Field `PortInt` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `PORT_INT0` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt0R = crate::BitReader;
#[doc = "Field `PORT_INT0` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT1` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt1R = crate::BitReader;
#[doc = "Field `PORT_INT1` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT2` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt2R = crate::BitReader;
#[doc = "Field `PORT_INT2` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT3` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt3R = crate::BitReader;
#[doc = "Field `PORT_INT3` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT4` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt4R = crate::BitReader;
#[doc = "Field `PORT_INT4` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P80Int` reader - If set to 1, Port80 will interrupt main processor on update from Host."]
pub type P80intR = crate::BitReader;
#[doc = "Field `P80Int` writer - If set to 1, Port80 will interrupt main processor on update from Host."]
Expand Down Expand Up @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader;
#[doc = "Field `GPIO` writer - If 1, when ESPICFG GPIO changes input value, will interrupt main processor."]
pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int(&self) -> PortIntR {
PortIntR::new((self.bits & 0x1f) as u8)
pub fn port_int0(&self) -> PortInt0R {
PortInt0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int1(&self) -> PortInt1R {
PortInt1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int2(&self) -> PortInt2R {
PortInt2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int3(&self) -> PortInt3R {
PortInt3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int4(&self) -> PortInt4R {
PortInt4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."]
#[inline(always)]
Expand Down Expand Up @@ -80,22 +116,46 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTENSET")
.field("port_int", &self.port_int())
.field("p80int", &self.p80int())
.field("bus_rst", &self.bus_rst())
.field("irq_upd", &self.irq_upd())
.field("wire_chg", &self.wire_chg())
.field("hstall", &self.hstall())
.field("crcerr", &self.crcerr())
.field("gpio", &self.gpio())
.field("port_int0", &self.port_int0())
.field("port_int1", &self.port_int1())
.field("port_int2", &self.port_int2())
.field("port_int3", &self.port_int3())
.field("port_int4", &self.port_int4())
.finish()
}
}
impl W {
#[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int0(&mut self) -> PortInt0W<IntensetSpec> {
PortInt0W::new(self, 0)
}
#[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int1(&mut self) -> PortInt1W<IntensetSpec> {
PortInt1W::new(self, 1)
}
#[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int2(&mut self) -> PortInt2W<IntensetSpec> {
PortInt2W::new(self, 2)
}
#[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int3(&mut self) -> PortInt3W<IntensetSpec> {
PortInt3W::new(self, 3)
}
#[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int(&mut self) -> PortIntW<IntensetSpec> {
PortIntW::new(self, 0)
pub fn port_int4(&mut self) -> PortInt4W<IntensetSpec> {
PortInt4W::new(self, 4)
}
#[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."]
#[inline(always)]
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82 changes: 71 additions & 11 deletions src/espi/intstat.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,26 @@
pub type R = crate::R<IntstatSpec>;
#[doc = "Register `INTSTAT` writer"]
pub type W = crate::W<IntstatSpec>;
#[doc = "Field `PortInt` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortIntR = crate::FieldReader;
#[doc = "Field `PortInt` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `PORT_INT0` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt0R = crate::BitReader;
#[doc = "Field `PORT_INT0` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT1` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt1R = crate::BitReader;
#[doc = "Field `PORT_INT1` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT2` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt2R = crate::BitReader;
#[doc = "Field `PORT_INT2` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT3` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt3R = crate::BitReader;
#[doc = "Field `PORT_INT3` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PORT_INT4` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt4R = crate::BitReader;
#[doc = "Field `PORT_INT4` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"]
pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P80Int` reader - If set to 1, Port80 will interrupt main processor on update from Host."]
pub type P80intR = crate::BitReader;
#[doc = "Field `P80Int` writer - If set to 1, Port80 will interrupt main processor on update from Host."]
Expand Down Expand Up @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader;
#[doc = "Field `GPIO` writer - If 1, when ESPICFG GPIO changes input value, will interrupt main processor."]
pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int(&self) -> PortIntR {
PortIntR::new((self.bits & 0x1f) as u8)
pub fn port_int0(&self) -> PortInt0R {
PortInt0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int1(&self) -> PortInt1R {
PortInt1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int2(&self) -> PortInt2R {
PortInt2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int3(&self) -> PortInt3R {
PortInt3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int4(&self) -> PortInt4R {
PortInt4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."]
#[inline(always)]
Expand Down Expand Up @@ -80,22 +116,46 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTSTAT")
.field("port_int", &self.port_int())
.field("p80int", &self.p80int())
.field("bus_rst", &self.bus_rst())
.field("irq_upd", &self.irq_upd())
.field("wire_chg", &self.wire_chg())
.field("hstall", &self.hstall())
.field("crcerr", &self.crcerr())
.field("gpio", &self.gpio())
.field("port_int0", &self.port_int0())
.field("port_int1", &self.port_int1())
.field("port_int2", &self.port_int2())
.field("port_int3", &self.port_int3())
.field("port_int4", &self.port_int4())
.finish()
}
}
impl W {
#[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int0(&mut self) -> PortInt0W<IntstatSpec> {
PortInt0W::new(self, 0)
}
#[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int1(&mut self) -> PortInt1W<IntstatSpec> {
PortInt1W::new(self, 1)
}
#[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int2(&mut self) -> PortInt2W<IntstatSpec> {
PortInt2W::new(self, 2)
}
#[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int3(&mut self) -> PortInt3W<IntstatSpec> {
PortInt3W::new(self, 3)
}
#[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"]
#[inline(always)]
pub fn port_int(&mut self) -> PortIntW<IntstatSpec> {
PortIntW::new(self, 0)
pub fn port_int4(&mut self) -> PortInt4W<IntstatSpec> {
PortInt4W::new(self, 4)
}
#[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."]
#[inline(always)]
Expand Down
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