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espi: put all ports into a single cluster repeated 5 times
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Signed-off-by: Felipe Balbi <[email protected]>
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Felipe Balbi committed Dec 5, 2024
1 parent 3715695 commit 253ba9f
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Showing 11 changed files with 1,051 additions and 240 deletions.
204 changes: 21 additions & 183 deletions patch/espi.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,200 +7,38 @@ ESPI:
BASE1: [1, Uses BASE1 offset in host memory (see MAPBASE reg)]
BASE2: [2, Uses BASE2 offset in host memory (see MAPBASE reg)]

_modify:
# Add missing descriptions
P[01234]CFG:
description: Port Configuration and Control
P[01234]STAT:
description: Port Status
P[01234]IRuleStat:
description: Port set Interrupt rules and user status
P[01234]ADDR:
description: Port address offset to host
P[01234]OMFLEN:
description: Port OOB, Mastering and Flash Length (for OOB, Bus Mastering, and Flash)
P[01234]DataIn:
description: Port Data from Host
P[01234]DataOut:
description: Port Data to Host (for Endpoint and Index/Data)
P[01234]RAMUse:
description: Port RAM base and size (for Mailbox and Bus Master)

# Rename registers to match documentation
P0DataIn:
name: P0DATAIN
P1DataIn:
name: P1DATAIN
P2DataIn:
name: P2DATAIN
P3DataIn:
name: P3DATAIN
P4DataIn:
name: P4DATAIN

P0DataOut:
name: P0DATAOUT
P1DataOut:
name: P1DATAOUT
P2DataOut:
name: P2DATAOUT
P3DataOut:
name: P3DATAOUT
P4DataOut:
name: P4DATAOUT

P0IRuleStat:
name: P0IRULESTAT
P1IRuleStat:
name: P1IRULESTAT
P2IRuleStat:
name: P2IRULESTAT
P3IRuleStat:
name: P3IRULESTAT
P4IRuleStat:
name: P4IRULESTAT

P0RAMUse:
name: P0RAMUSE
P1RAMUse:
name: P1RAMUSE
P2RAMUse:
name: P2RAMUSE
P3RAMUse:
name: P3RAMUSE
P4RAMUse:
name: P4RAMUSE

# Derive registers from one another
_derive:
P1CFG: "ESPI.PORT0.CFG"
P2CFG: "ESPI.PORT0.CFG"
P3CFG: "ESPI.PORT0.CFG"
P4CFG: "ESPI.PORT0.CFG"

P1STAT: "ESPI.PORT0.STAT"
P2STAT: "ESPI.PORT0.STAT"
P3STAT: "ESPI.PORT0.STAT"
P4STAT: "ESPI.PORT0.STAT"

P1IRULESTAT: "ESPI.PORT0.IRULESTAT"
P2IRULESTAT: "ESPI.PORT0.IRULESTAT"
P3IRULESTAT: "ESPI.PORT0.IRULESTAT"
P4IRULESTAT: "ESPI.PORT0.IRULESTAT"

P1ADDR: "ESPI.PORT0.ADDR"
P2ADDR: "ESPI.PORT0.ADDR"
P3ADDR: "ESPI.PORT0.ADDR"
P4ADDR: "ESPI.PORT0.ADDR"

P1OMFLEN: "ESPI.PORT0.OMFLEN"
P2OMFLEN: "ESPI.PORT0.OMFLEN"
P3OMFLEN: "ESPI.PORT0.OMFLEN"
P4OMFLEN: "ESPI.PORT0.OMFLEN"

P1DATAIN: "ESPI.PORT0.DATAIN"
P2DATAIN: "ESPI.PORT0.DATAIN"
P3DATAIN: "ESPI.PORT0.DATAIN"
P4DATAIN: "ESPI.PORT0.DATAIN"

P1DATAOUT: "ESPI.PORT0.DATAOUT"
P2DATAOUT: "ESPI.PORT0.DATAOUT"
P3DATAOUT: "ESPI.PORT0.DATAOUT"
P4DATAOUT: "ESPI.PORT0.DATAOUT"

P1RAMUSE: "ESPI.PORT0.RAMUSE"
P2RAMUSE: "ESPI.PORT0.RAMUSE"
P3RAMUSE: "ESPI.PORT0.RAMUSE"
P4RAMUSE: "ESPI.PORT0.RAMUSE"

# Create Port Clusters
_cluster:
PORT0:
P0CFG:
PORT%s:
description: "Port 0-4"
P[01234]CFG:
description: Port Configuration and Control
name: CFG
P0STAT:
name: STAT
P0IRULESTAT:
name: IRULESTAT
P0ADDR:
name: ADDR
P0OMFLEN:
name: OMFLEN
P0DATAIN:
name: DATAIN
P0DATAOUT:
name: DATAOUT
P0RAMUSE:
name: RAMUSE

PORT1:
P1CFG:
name: CFG
P1STAT:
P[01234]STAT:
description: Port Status
name: STAT
P1IRULESTAT:

P[01234]IRuleStat:
description: Port set interrupt rules and user status
name: IRULESTAT
P1ADDR:
name: ADDR
P1OMFLEN:
name: OMFLEN
P1DATAIN:
name: DATAIN
P1DATAOUT:
name: DATAOUT
P1RAMUSE:
name: RAMUSE

PORT2:
P2CFG:
name: CFG
P2STAT:
name: STAT
P2IRULESTAT:
name: IRULESTAT
P2ADDR:
P[01234]ADDR:
description: Port Address offset to host
name: ADDR
P2OMFLEN:
name: OMFLEN
P2DATAIN:
name: DATAIN
P2DATAOUT:
name: DATAOUT
P2RAMUSE:
name: RAMUSE

PORT3:
P3CFG:
name: CFG
P3STAT:
name: STAT
P3IRULESTAT:
name: IRULESTAT
P3ADDR:
name: ADDR
P3OMFLEN:
P[01234]OMFLEN:
description: Port OOB, Mastering and Flash Length (for OOB, Bus Mastering, and Flash)
name: OMFLEN
P3DATAIN:
name: DATAIN
P3DATAOUT:
name: DATAOUT
P3RAMUSE:
name: RAMUSE

PORT4:
P4CFG:
name: CFG
P4STAT:
name: STAT
P4IRULESTAT:
name: IRULESTAT
P4ADDR:
name: ADDR
P4OMFLEN:
name: OMFLEN
P4DATAIN:
P[01234]DataIn:
description: Port Data from Host
name: DATAIN
P4DATAOUT:

P[01243]DataOut:
description: Port Data to Host (for Endpoint and Index/Data)
name: DATAOUT
P4RAMUSE:

P[01234]RAMUse:
description: Port RAM base and size (for Mailbox and Bus Master)
name: RAMUSE
86 changes: 29 additions & 57 deletions src/espi.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,15 +21,7 @@ pub struct RegisterBlock {
espicfg: Espicfg,
espimisc: Espimisc,
_reserved16: [u8; 0xb4],
port0: Port0,
_reserved17: [u8; 0x08],
port1: Port1,
_reserved18: [u8; 0x08],
port2: Port2,
_reserved19: [u8; 0x08],
port3: Port3,
_reserved20: [u8; 0x08],
port4: Port4,
port: (),
}
impl RegisterBlock {
#[doc = "0x00 - Master Control for whole peripheral"]
Expand Down Expand Up @@ -112,30 +104,30 @@ impl RegisterBlock {
pub const fn espimisc(&self) -> &Espimisc {
&self.espimisc
}
#[doc = "0x100..0x118 - Cluster PORT0, containing P0CFG, P0STAT, P0IRULESTAT, P0ADDR, P0OMFLEN, P0DATAIN, P0DATAOUT, P0RAMUSE"]
#[inline(always)]
pub const fn port0(&self) -> &Port0 {
&self.port0
}
#[doc = "0x120..0x138 - Cluster PORT1, containing P1CFG, P1STAT, P1IRULESTAT, P1ADDR, P1OMFLEN, P1DATAIN, P1DATAOUT, P1RAMUSE"]
#[inline(always)]
pub const fn port1(&self) -> &Port1 {
&self.port1
}
#[doc = "0x140..0x158 - Cluster PORT2, containing P2CFG, P2STAT, P2IRULESTAT, P2ADDR, P2OMFLEN, P2DATAIN, P2DATAOUT, P2RAMUSE"]
#[inline(always)]
pub const fn port2(&self) -> &Port2 {
&self.port2
}
#[doc = "0x160..0x178 - Cluster PORT3, containing P3CFG, P3STAT, P3IRULESTAT, P3ADDR, P3OMFLEN, P3DATAIN, P3DATAOUT, P3RAMUSE"]
#[inline(always)]
pub const fn port3(&self) -> &Port3 {
&self.port3
}
#[doc = "0x180..0x198 - Cluster PORT4, containing P4CFG, P4STAT, P4IRULESTAT, P4ADDR, P4OMFLEN, P4DATAIN, P4DATAOUT, P4RAMUSE"]
#[inline(always)]
pub const fn port4(&self) -> &Port4 {
&self.port4
#[doc = "0x100..0x178 - Port 0-4"]
#[inline(always)]
pub const fn port(&self, n: usize) -> &Port {
#[allow(clippy::no_effect)]
[(); 5][n];
unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(256)
.add(32 * n)
.cast()
}
}
#[doc = "Iterator for array of:"]
#[doc = "0x100..0x178 - Port 0-4"]
#[inline(always)]
pub fn port_iter(&self) -> impl Iterator<Item = &Port> {
(0..5).map(move |n| unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(256)
.add(32 * n)
.cast()
})
}
}
#[doc = "MCTRL (rw) register accessor: Master Control for whole peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl`]
Expand Down Expand Up @@ -234,28 +226,8 @@ module"]
pub type Espimisc = crate::Reg<espimisc::EspimiscSpec>;
#[doc = "Miscellaneous uses, such as Alert pin as GPIO (when not used for Alert)."]
pub mod espimisc;
#[doc = "Cluster PORT0, containing P0CFG, P0STAT, P0IRULESTAT, P0ADDR, P0OMFLEN, P0DATAIN, P0DATAOUT, P0RAMUSE"]
pub use self::port0::Port0;
#[doc = r"Cluster"]
#[doc = "Cluster PORT0, containing P0CFG, P0STAT, P0IRULESTAT, P0ADDR, P0OMFLEN, P0DATAIN, P0DATAOUT, P0RAMUSE"]
pub mod port0;
#[doc = "Cluster PORT1, containing P1CFG, P1STAT, P1IRULESTAT, P1ADDR, P1OMFLEN, P1DATAIN, P1DATAOUT, P1RAMUSE"]
pub use self::port1::Port1;
#[doc = r"Cluster"]
#[doc = "Cluster PORT1, containing P1CFG, P1STAT, P1IRULESTAT, P1ADDR, P1OMFLEN, P1DATAIN, P1DATAOUT, P1RAMUSE"]
pub mod port1;
#[doc = "Cluster PORT2, containing P2CFG, P2STAT, P2IRULESTAT, P2ADDR, P2OMFLEN, P2DATAIN, P2DATAOUT, P2RAMUSE"]
pub use self::port2::Port2;
#[doc = r"Cluster"]
#[doc = "Cluster PORT2, containing P2CFG, P2STAT, P2IRULESTAT, P2ADDR, P2OMFLEN, P2DATAIN, P2DATAOUT, P2RAMUSE"]
pub mod port2;
#[doc = "Cluster PORT3, containing P3CFG, P3STAT, P3IRULESTAT, P3ADDR, P3OMFLEN, P3DATAIN, P3DATAOUT, P3RAMUSE"]
pub use self::port3::Port3;
#[doc = r"Cluster"]
#[doc = "Cluster PORT3, containing P3CFG, P3STAT, P3IRULESTAT, P3ADDR, P3OMFLEN, P3DATAIN, P3DATAOUT, P3RAMUSE"]
pub mod port3;
#[doc = "Cluster PORT4, containing P4CFG, P4STAT, P4IRULESTAT, P4ADDR, P4OMFLEN, P4DATAIN, P4DATAOUT, P4RAMUSE"]
pub use self::port4::Port4;
#[doc = "Port 0-4"]
pub use self::port::Port;
#[doc = r"Cluster"]
#[doc = "Cluster PORT4, containing P4CFG, P4STAT, P4IRULESTAT, P4ADDR, P4OMFLEN, P4DATAIN, P4DATAOUT, P4RAMUSE"]
pub mod port4;
#[doc = "Port 0-4"]
pub mod port;
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