add bufered uart

OpenDevicePartnership · Feb 14, 2025 · eaa1c7a · eaa1c7a
1 parent 3667499
commit eaa1c7a
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Showing 4 changed files with 393 additions and 28 deletions.
diff --git a/src/dma/channel.rs b/src/dma/channel.rs
@@ -124,24 +124,6 @@ impl<'d> Channel<'d> {
         let xfercount = (mem_len / xferwidth) - 1;
         let channel = self.info.ch_num;
 
-        // Configure the channel descriptor
-        // NOTE: the DMA controller expects the memory buffer end address but peripheral address is actual
-        // SAFETY: unsafe due to use of a mutable static (DESCRIPTORS.list)
-        unsafe {
-            DESCRIPTORS.list[channel].reserved = 0;
-            if dir == Direction::MemoryToPeripheral {
-                DESCRIPTORS.list[channel].dst_data_end_addr = dstbase as u32;
-            } else {
-                DESCRIPTORS.list[channel].dst_data_end_addr = dstbase as u32 + (xfercount * xferwidth) as u32;
-            }
-            if dir == Direction::PeripheralToMemory {
-                DESCRIPTORS.list[channel].src_data_end_addr = srcbase as u32;
-            } else {
-                DESCRIPTORS.list[channel].src_data_end_addr = srcbase as u32 + (xfercount * xferwidth) as u32;
-            }
-            DESCRIPTORS.list[channel].nxt_desc_link_addr = 0;
-        }
-
         // Configure for transfer type, no hardware triggering (we'll trigger via software), high priority
         // SAFETY: unsafe due to .bits usage
         self.info.regs.channel(channel).cfg().write(|w| unsafe {
@@ -164,8 +146,19 @@ impl<'d> Channel<'d> {
         // SAFETY: unsafe due to .bits usage
         self.info.regs.channel(channel).xfercfg().write(|w| unsafe {
             w.cfgvalid().set_bit();
-            w.clrtrig().set_bit();
-            w.reload().clear_bit();
+
+            if options.is_continuous {
+                w.reload().enabled();
+                w.clrtrig().clear_bit();
+            } else {
+                w.reload().disabled();
+                w.clrtrig().set_bit();
+            }
+            if options.is_sw_trig {
+                w.swtrig().set_bit();
+            } else {
+                w.swtrig().clear_bit();
+            }
             w.setinta().set_bit();
             w.width().bits(options.width.into());
             if dir == Direction::PeripheralToMemory {
@@ -180,6 +173,35 @@ impl<'d> Channel<'d> {
             }
             w.xfercount().bits(xfercount as u16)
         });
+
+        // Configure the channel descriptor
+        // NOTE: the DMA controller expects the memory buffer end address but peripheral address is actual
+        // SAFETY: unsafe due to use of a mutable static (DESCRIPTORS.list)
+        unsafe {
+            if options.is_continuous {
+                let xfer_cfg = self.info.regs.channel(channel).xfercfg().read();
+                DESCRIPTORS.list[channel].reserved_reloadcfg = xfer_cfg.bits();
+            } else {
+                DESCRIPTORS.list[channel].reserved_reloadcfg = 0;
+            }
+
+            if dir == Direction::MemoryToPeripheral {
+                DESCRIPTORS.list[channel].dst_data_end_addr = dstbase as u32;
+            } else {
+                DESCRIPTORS.list[channel].dst_data_end_addr = dstbase as u32 + (xfercount * xferwidth) as u32;
+            }
+
+            if dir == Direction::PeripheralToMemory {
+                DESCRIPTORS.list[channel].src_data_end_addr = srcbase as u32;
+            } else {
+                DESCRIPTORS.list[channel].src_data_end_addr = srcbase as u32 + (xfercount * xferwidth) as u32;
+            }
+            if options.is_continuous {
+                DESCRIPTORS.list[channel].nxt_desc_link_addr = &DESCRIPTORS.list[channel] as *const _ as u32;
+            } else {
+                DESCRIPTORS.list[channel].nxt_desc_link_addr = 0;
+            }
+        }
     }
 
     /// Enable the DMA channel (only after configuring)
@@ -192,6 +214,40 @@ impl<'d> Channel<'d> {
             .modify(|_, w| unsafe { w.ena().bits(1 << channel) });
     }
 
+    #[cfg(feature = "defmt")]
+    /// Log the DMA channel transfer configuration
+    pub fn log_channel(&self) {
+        // Log DMA Channel Config Register
+        let channel = self.info.ch_num;
+        let dma_channel_cfg = self.info.regs.channel(channel).cfg().read();
+        defmt::info!(
+            "DMA Channel {} Config Register: 0x{=u32:x}",
+            channel,
+            dma_channel_cfg.bits()
+        );
+        // Log Interrupt Enable Set Register
+        let intenset0 = self.info.regs.intenset0().read();
+        defmt::info!("Interrupt Enable Set Register: 0x{=u32:x}", intenset0.bits());
+
+        // Log DMA Xfer Config Register
+        let xfer_cfg = self.info.regs.channel(channel).xfercfg().read();
+        defmt::info!(
+            "DMA Channel {} Xfer Config Register: 0x{=u32:x}",
+            channel,
+            xfer_cfg.bits()
+        );
+        // Log DMA Enable Set Register after enabling
+        let enableset0 = self.info.regs.enableset0().read();
+        defmt::info!("DMA Enable Set Register:0x{=u32:x}", enableset0.bits());
+        // Log DMA Xfer Config Register after triggering
+        let xfer_cfg_after = self.info.regs.channel(channel).xfercfg().read();
+        defmt::info!(
+            "DMA Channel {} Xfer Config Register (After Trigger): 0x{=u32:x}",
+            channel,
+            xfer_cfg_after.bits()
+        );
+    }
+
     /// Disable the DMA channel
     pub fn disable_channel(&self) {
         let channel = self.info.ch_num;

diff --git a/src/dma/mod.rs b/src/dma/mod.rs
@@ -26,7 +26,7 @@ const DMA_CHANNEL_COUNT: usize = 33;
 #[derive(Copy, Clone, Debug)]
 #[repr(C)]
 struct ChannelDescriptor {
-    reserved: u32,
+    reserved_reloadcfg: u32,
     src_data_end_addr: u32,
     dst_data_end_addr: u32,
     nxt_desc_link_addr: u32,
@@ -42,7 +42,7 @@ struct DescriptorBlock {
 /// DMA channel descriptor list
 static mut DESCRIPTORS: DescriptorBlock = DescriptorBlock {
     list: [ChannelDescriptor {
-        reserved: 0,
+        reserved_reloadcfg: 0,
         src_data_end_addr: 0,
         dst_data_end_addr: 0,
         nxt_desc_link_addr: 0,

diff --git a/src/dma/transfer.rs b/src/dma/transfer.rs
@@ -16,13 +16,21 @@ pub struct TransferOptions {
 
     /// Transfer priority level
     pub priority: Priority,
+
+    /// Transfer is intended to be done continuously, such as for a circular buffer
+    pub is_continuous: bool,
+
+    /// Transfer is software triggerred
+    pub is_sw_trig: bool,
 }
 
 impl Default for TransferOptions {
     fn default() -> Self {
         Self {
             width: Width::Bit8,
             priority: Priority::Priority0,
+            is_continuous: false,
+            is_sw_trig: false,
         }
     }
 }