Fixed: Message on check against sau num regions = 0

[thorstendb-ARM]

Fixed.
Checking sauNumRegions against sauRegion config:

• if set > 0 and regions are present: compare number against number of regions. If there are moire regions than set, warning:

*** WARNING M391: /Users/thode01/work/github/devtools/build/tools/svdconv/SVDConv/darwin-arm64/Debug/ARMCM23.svd (Line 56) 
  CPU: configured num of SAU regions '4' greater than <sauNumRegions> value: 1

• if set to 0 and regions are present, error:

*** ERROR M387: /Users/thode01/work/github/devtools/build/tools/svdconv/SVDConv/darwin-arm64/Debug/ARMCM23.svd (Line 56) 
  CPU: <sauNumRegions> set to null but regions are configured.

Testfile:

<?xml version="1.0" encoding="utf-8"?>

<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->
  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->
  <name>ARMCM23</name>                                            <!-- name of part-->
  <series>ARMv8-M Baseline</series>                               <!-- device series the device belongs to -->
  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
  <description>ARM 32-bit Cortex-M23 based device.</description>
  <licenseText>                                                   <!-- this license text will appear in header file. \n force line breaks -->
    ARM Limited (ARM) is supplying this software for use with Cortex-M\n
    processor based microcontroller, but can be equally used for other\n
    suitable  processor architectures. This file can be freely distributed.\n
    Modifications to this file shall be clearly marked.\n
    \n
    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  </licenseText>

  <cpu>                                                           <!-- details about the cpu embedded in the device -->
    <name>CM23</name>
    <revision>r0p0</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <vtorPresent>true</vtorPresent>
    <nvicPrioBits>3</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
    <sauNumRegions>0</sauNumRegions>
    <sauRegionsConfig enabled="true" protectionWhenDisabled="s">
      <region enabled="true" name="SauRegion0">
        <base>0x00000000</base>
        <limit>0x001FFFE0</limit>
        <!-- secure / non-secure callable -->
        <access>c</access>
      </region>
      <region enabled="true" name="SauRegion1">
        <base>0x00200000</base>
        <limit>0x003FFFE0</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
      <region enabled="true" name="SauRegion2">
        <base>0x20200000</base>
        <limit>0x203FFFE0</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
      <region enabled="true" name="SauRegion3">
        <base>0x40000000</base>
        <limit>0x40040000</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
    </sauRegionsConfig>
  </cpu>

  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
  <width>32</width>                                               <!-- bus width is 32 bits -->
  <!-- default settings implicitly inherited by subsequent sections -->
  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
                                                                       and register that do not define "size" themselves -->
  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->

</device>

[github-actions]

Test Results

 6 files  12 suites   0s ⏱️
26 tests 26 ✅ 0 💤 0 ❌
78 runs  78 ✅ 0 💤 0 ❌

Results for commit 384117a.

♻️ This comment has been updated with latest results.

[jkrech]

LGTM

[jkrech]

Please take a look at the comments.

[codecov]

Codecov Report

Attention: Patch coverage is 16.66667% with 5 lines in your changes missing coverage. Please review.

Project coverage is 63.54%. Comparing base (2ba9658) to head (384117a).

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #1582      +/-   ##
==========================================
- Coverage   63.55%   63.54%   -0.01%     
==========================================
  Files         162      162              
  Lines       31237    31242       +5     
  Branches    19147    19151       +4     
==========================================
+ Hits        19852    19853       +1     
- Misses       7497     7556      +59     
+ Partials     3888     3833      -55     

Flag	Coverage Δ
svdconv-cov	39.77% <16.66%> (-0.01%)	⬇️

Flags with carried forward coverage won't be shown. Click here to find out more.

Files	Coverage Δ
tools/svdconv/SVDModel/src/SvdCpu.cpp	39.58% <16.66%> (-0.42%)	⬇️

... and 12 files with indirect coverage changes

[jkrech]

LGTM