drivers: sam: update to support sama7g5 PDMC peripheral #7228
Conversation
There was a problem hiding this comment.
Acked-by: Etienne Carriere <[email protected]> for commits
"drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks",
"drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0",
"drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers" (s/wrote/written/ and s/Setting/Set/ in commit message),
"drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks" and
"plat-sam: add sama7g5's PDMC gclk clocks to the SCMI clock list".
core/arch/arm/plat-sam/scmi_server.c
Outdated
| @@ -1116,6 +1117,46 @@ size_t plat_scmi_rd_count(unsigned int channel_id) | |||
| return resource->rd_count; | |||
| } | |||
|
|
|||
| void sam_set_clock_range(unsigned int pmc_type, unsigned int pmc_id, | |||
| const struct clk_range *output) | |||
There was a problem hiding this comment.
this is rather an input argument. Maybe prefer range as variable name.
but that's not a strong opinion.
core/arch/arm/plat-sam/scmi_server.c
Outdated
| @@ -111,10 +111,11 @@ struct sam_pmc_clk { | |||
| unsigned int scmi_id; | |||
| unsigned int pmc_type; | |||
| unsigned int pmc_id; | |||
| struct clk_range output; | |||
There was a problem hiding this comment.
range or output_range?
core/arch/arm/plat-sam/scmi_server.c
Outdated
| unsigned int i = 0; | ||
|
|
||
| if (channel_id == 0) { | ||
| for (i = 0; i < ARRAY_SIZE(pmc_clks); i++, p++) { |
There was a problem hiding this comment.
nitpicking: p initialization should preferably be in the for instruction.
Maybe for (p = pmc_clks; p < pmc_clks + ARRAY_SIZE(pmc_clks); p++) { is enougth.
`
| p->output.max = output->max; | ||
| return; | ||
| } | ||
| } |
There was a problem hiding this comment.
no issue if clock is not found?
There was a problem hiding this comment.
No side effects when a clock has the range but it's not included in the SCMI clock list.
Add clock range attribute to the struct for the clocks. New function for initializing the clock range for the clocks. Implement "plat_scmi_clock_rates_by_step()" to be used by SCMI. Signed-off-by: Tony Han <[email protected]>
… clocks Initialize the clock range values for sama7g5 clocks so that they can be used in responding SCMI CLOCK_DESCRIBE_RATES command. Signed-off-by: Tony Han <[email protected]> Acked-by: Etienne Carriere <[email protected]>
Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0 peripheral. Signed-off-by: Tony Han <[email protected]> Acked-by: Etienne Carriere <[email protected]>
When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx. Fixes: 4318c69 ("drivers: clk: sam: add PLL clock driver for sama7g5") Signed-off-by: Tony Han <[email protected]> Acked-by: Etienne Carriere <[email protected]>
Fix the underflow of the divider calculated when clock given rate is greater than the rate of the clock parent. Fixes: 4318c69 ("drivers: clk: sam: add PLL clock driver for sama7g5") Signed-off-by: Tony Han <[email protected]> Acked-by: Etienne Carriere <[email protected]>
Add PDMC gclk clocks to the SCMI clock list so that they could be used outside OP-TEE OS. Signed-off-by: Tony Han <[email protected]> Acked-by: Etienne Carriere <[email protected]>
…GCLK Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral. Signed-off-by: Tony Han <[email protected]>
|
Updated according to the comments and add an extra commit for supporting I2SMCC peripheral, thank you very much. |
The commits includes: