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version 0.2.4
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@Nitcloud
Nitcloud committed May 31, 2022
1 parent 2bccd0f commit 5b97f6d
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0 ...ib/Hardware/Apply/DSP/Advance/AGC/AGC.PNG → ...om/Hardware/Apply/DSP/Advance/AGC/AGC.PNG
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0 ..._lib/Hardware/Apply/DSP/Advance/AGC/AGC.v → lib/com/Hardware/Apply/DSP/Advance/AGC/AGC.v
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48 changes: 18 additions & 30 deletions ...ce/Communicate/Demodulate/IQ/Demodulate.v → ...ce/Communicate/Demodulate/IQ/Demodulate.v
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Original file line number Diff line number Diff line change
@@ -1,12 +1,13 @@
module Demodule #(
module Demodulate #(
parameter PHASE_WIDTH = 32,
parameter Fiter_WIDTH = 38,
parameter INPUT_WIDTH = 8,
parameter OUTPUT_WIDTH = 12
) (
input clk_in,
input clk,
input RST,

input [15:0] FACTOR,
input [PHASE_WIDTH-1:0] Fre_word,

input [INPUT_WIDTH-1:0] wave_in,
Expand All @@ -16,44 +17,31 @@ module Demodule #(
output [OUTPUT_WIDTH-1:0] AM_Demodule_OUT
);

/*
10.7MHz 带通滤波器100M的采样率, 1M的通带
*/
wire [22:0] filter_out;
FIR_100M_10_7M_BPF u_FIR_100M_10_7M_BPF(
//ports
.clk ( clk_in ),
.clk_enable ( 1'b1 ),
.reset ( RST ),
.filter_in ( wave_in ),
.filter_out ( filter_out )
);

/*
数字下变频处理模块
*/
// IQ_MIXED Outputs
wire clk_out;
wire [OUTPUT_WIDTH - 1 : 0] I_OUT;
wire [OUTPUT_WIDTH - 1 : 0] Q_OUT;

/*
数字下变频处理模块
*/
IQ_MIXED #(
.LO_WIDTH ( 12 ),
.PHASE_WIDTH ( PHASE_WIDTH ),
.Fiter_WIDTH ( Fiter_WIDTH ),
.INPUT_WIDTH ( INPUT_WIDTH ),
.OUTPUT_WIDTH ( OUTPUT_WIDTH ))
u_IQ_MIXED (
.clk_in ( clk_in ),
.clk_out ( clk_out ),
.RST ( RST ),
.clk ( clk ),
.clk_out ( clk_out ),
.RST ( RST ),

.FACTOR ( FACTOR ),
.Fre_word ( Fre_word ),
.FACTOR ( FACTOR ),
.Fre_word ( Fre_word ),

.wave_in ( filter_out[22:11] ),
.I_OUT ( I_OUT ),
.Q_OUT ( Q_OUT )
.wave_in ( wave_in ),
.I_OUT ( I_OUT ),
.Q_OUT ( Q_OUT )
);

wire [OUTPUT_WIDTH-1:0] Y_diff;
Expand All @@ -62,8 +50,8 @@ Cordic # (
.PH_BITS(OUTPUT_WIDTH), //1~32
.ITERATIONS(16), //1~32
.CORDIC_STYLE("VECTOR")) //ROTATE //VECTOR
Demodule_Gen_u (
.clk_in(clk_out),
Demodulate_Gen_u (
.clk(clk_out),
.RST(RST),
.x_i(I_OUT),
.y_i(Q_OUT),
Expand All @@ -75,10 +63,10 @@ Demodule_Gen_u (
.phase_out(PM_Demodule_OUT)
);

reg [OUTPUT_WIDTH-1:0] PM_Demodule_OUT_r;
reg [OUTPUT_WIDTH-1:0] PM_Demodule_OUT_r = 0;
always @(posedge clk_out) begin
PM_Demodule_OUT_r <= PM_Demodule_OUT;
end
assign FM_Demodule_OUT = $signed(PM_Demodule_OUT) - $signed(PM_Demodule_OUT_r);

endmodule
endmodule
29 changes: 13 additions & 16 deletions ...ance/Communicate/Demodulate/IQ/IQ_Mixed.v → ...ance/Communicate/Demodulate/IQ/IQ_Mixed.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3,37 +3,34 @@ module IQ_MIXED #(
parameter LO_WIDTH = 12,
parameter PHASE_WIDTH = 32,
//CIC_Filter_parameter
parameter FACTOR = 10,
parameter Fiter_WIDTH = 38,
//IQ_MIXED_parameter
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
) (
input clk_in,
input clk,
output clk_out,
input RST,

input [15:0] FACTOR,
input [PHASE_WIDTH - 1 : 0] Fre_word,

input [INPUT_WIDTH - 1 : 0] wave_in,
output [OUTPUT_WIDTH - 1 : 0] I_OUT,
output [OUTPUT_WIDTH - 1 : 0] Q_OUT
);

/*
Orthogonal signal generator, using rotation mode, enabling phase accumulator
*/
wire [LO_WIDTH-1:0] cos_wave;
wire [LO_WIDTH-1:0] sin_wave;
wire [PHASE_WIDTH-1:0] pha_diff;
Cordic # (
.XY_BITS(LO_WIDTH),
.PH_BITS(PHASE_WIDTH), //1~32
.ITERATIONS(16), //1~32
.ITERATIONS(16), //1~32
.CORDIC_STYLE("ROTATE"), //ROTATE //VECTOR
.PHASE_ACC("ON") //ON //OFF
) IQ_Gen_u (
.clk_in(clk_in),
.clk(clk),
.RST(RST),
.x_i(0),
.y_i(0),
Expand All @@ -49,7 +46,7 @@ wire signed [Fiter_WIDTH - 1 : 0] I_SIG;
wire signed [Fiter_WIDTH - 1 : 0] Q_SIG;
reg signed [INPUT_WIDTH + LO_WIDTH - 1 : 0] I_SIG_r = 0;
reg signed [INPUT_WIDTH + LO_WIDTH - 1 : 0] Q_SIG_r = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
I_SIG_r <= 24'd0;
Q_SIG_r <= 24'd0;
Expand All @@ -64,28 +61,28 @@ assign Q_SIG = Q_SIG_r[INPUT_WIDTH + LO_WIDTH - 1 : INPUT_WIDTH + LO_WIDTH - 12]


wire [Fiter_WIDTH-1:0] Fiter_wave_I;
CIC_DOWN_S3 #(
.FACTOR(FACTOR),
CIC_DOWN_S3#(
.INPUT_WIDTH(12),
.OUTPUT_WIDTH(Fiter_WIDTH)
) Fiter_I (
.clk(clk_in),
.OUTPUT_WIDTH(Fiter_WIDTH))
Fiter_I (
.clk(clk),
.clk_enable(1'd1),
.reset(RST),
.FACTOR(FACTOR),
.filter_in(I_SIG),
.filter_out(Fiter_wave_I)
);
assign I_OUT = Fiter_wave_I[Fiter_WIDTH - 1 : Fiter_WIDTH - OUTPUT_WIDTH];

wire [Fiter_WIDTH-1:0] Fiter_wave_Q;
CIC_DOWN_S3 #(
.FACTOR(FACTOR),
CIC_DOWN_S3#(
.INPUT_WIDTH(12),
.OUTPUT_WIDTH(Fiter_WIDTH)
) Fiter_Q(
.clk(clk_in),
.clk(clk),
.clk_enable(1'd1),
.reset(RST),
.FACTOR(FACTOR),
.filter_in(Q_SIG),
.filter_out(Fiter_wave_Q),
.ce_out(clk_out)
Expand Down
0 ...e/Communicate/Demodulate/IQ/Loop_filter.v → ...e/Communicate/Demodulate/IQ/Loop_filter.v
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0 ...P/Advance/Communicate/Encode/manchester.v → ...P/Advance/Communicate/Encode/manchester.v
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0 ...ply/DSP/Advance/Communicate/Encode/mseq.v → ...ply/DSP/Advance/Communicate/Encode/mseq.v
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40 changes: 21 additions & 19 deletions ...nce/Communicate/Modulate/AM/AM_Modulate.v → ...nce/Communicate/Modulate/AM/AM_Modulate.v
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@@ -1,21 +1,23 @@
`timescale 1ns / 1ps

module AM_Modulate #(
parameter INPUT_WIDTH = 12,
parameter PHASE_WIDTH = 32,
parameter DEEP_WIDTH = 16,
parameter OUTPUT_WIDTH = 12
) (
input clk_in,
input clk,
input RST,
input [INPUT_WIDTH - 1 : 0] wave_in,
input [15:0] module_deep, //(2^16-1)*percent
input [PHASE_WIDTH - 1 : 0] center_fre, //(fre*4294967296)/clk_in/1000000
input [INPUT_WIDTH - 1 : 0] wave_in,
input [PHASE_WIDTH - 1 : 0] center_fre, //(fre*2^PHASE_WIDTH)/Fc
input [DEEP_WIDTH - 1 : 0] modulate_deep,//(2^DEEP_WIDTH-1)*percent
output [OUTPUT_WIDTH - 1 : 0] AM_wave
);


localparam [INPUT_WIDTH - 1 : 0] DC_Value = 2**(INPUT_WIDTH-1);

reg [INPUT_WIDTH - 1 : 0] wave_in_r = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
wave_in_r <= 0;
end
Expand All @@ -24,43 +26,43 @@ always @(posedge clk_in) begin
end
end

reg signed [INPUT_WIDTH + 16 : 0] data_r0 = 0;
always @(posedge clk_in) begin
reg signed [INPUT_WIDTH + DEEP_WIDTH : 0] data_r0 = 0;
always @(posedge clk) begin
if (RST) begin
data_r0 <= 0;
end
else begin
data_r0 <= $signed(wave_in_r) * $signed({1'd0,module_deep});
data_r0 <= $signed(wave_in_r) * $signed({1'b0,modulate_deep});
end
end

reg signed [INPUT_WIDTH - 1 : 0] data_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
data_r1 <= 0;
end
else begin
data_r1 <= data_r0[INPUT_WIDTH + 15 : 16];
data_r1 <= data_r0[INPUT_WIDTH + DEEP_WIDTH - 1 : DEEP_WIDTH];
end
end

reg [INPUT_WIDTH - 1 : 0] data_r2 = 0;
always @(posedge clk_in) begin
reg [INPUT_WIDTH : 0] data_r2 = 0;
always @(posedge clk) begin
if (RST) begin
data_r2 <= 0;
end
else begin
data_r2 <= $signed(data_r1) + 12'd2048;
data_r2 <= $signed(data_r1) + $signed({1'b0,DC_Value});
end
end

reg [PHASE_WIDTH - 1 : 0] addr_r0 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
addr_r0 <= addr_r0 + center_fre;
end

reg [9:0] addr_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
addr_r1 <= addr_r0[PHASE_WIDTH - 1 : PHASE_WIDTH - 10];
end

Expand Down Expand Up @@ -348,7 +350,7 @@ always @(*) begin
end

reg signed [13 : 0] AM_Carry_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
AM_Carry_r1 <= 0;
end
Expand All @@ -358,7 +360,7 @@ always @(posedge clk_in) begin
end

reg signed [INPUT_WIDTH + 14 : 0] AM_wave_r0 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
AM_wave_r0 <= 0;
end
Expand All @@ -368,7 +370,7 @@ always @(posedge clk_in) begin
end

reg signed [OUTPUT_WIDTH - 1 : 0] AM_wave_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
AM_wave_r1 <= 0;
end
Expand Down
22 changes: 11 additions & 11 deletions ...nce/Communicate/Modulate/FM/FM_Modulate.v → ...nce/Communicate/Modulate/FM/FM_Modulate.v
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Expand Up @@ -4,16 +4,16 @@ module FM_Modulate #(
parameter PHASE_WIDTH = 32,
parameter OUTPUT_WIDTH = 12
) (
input clk_in,
input clk,
input RST,
input [INPUT_WIDTH - 1 : 0] wave_in,
input [PHASE_WIDTH - INPUT_WIDTH - 1 : 0] move_fre, //(fre*1048576)/clk_in/1000000
input [PHASE_WIDTH - 1 : 0] center_fre, //(fre*4294967296)/clk_in/1000000
input [PHASE_WIDTH - INPUT_WIDTH - 1 : 0] move_fre, //(fre*2^(PHASE_WIDTH-INPUT_WIDTH))/clk/1000000
input [PHASE_WIDTH - 1 : 0] center_fre, //(fre*2^PHASE_WIDTH)/clk/1000000
output [OUTPUT_WIDTH - 1 : 0] FM_wave
);

reg [INPUT_WIDTH - 1 : 0] wave_in_r = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
wave_in_r <= 0;
end
Expand All @@ -23,7 +23,7 @@ always @(posedge clk_in) begin
end

reg signed [PHASE_WIDTH : 0] data_r0 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
data_r0 <= 0;
end
Expand All @@ -33,7 +33,7 @@ always @(posedge clk_in) begin
end

reg signed [PHASE_WIDTH - 1 : 0] data_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
data_r1 <= 0;
end
Expand All @@ -43,7 +43,7 @@ always @(posedge clk_in) begin
end

reg signed [PHASE_WIDTH : 0] data_r2 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
data_r2 <= 0;
end
Expand All @@ -53,7 +53,7 @@ always @(posedge clk_in) begin
end

reg [PHASE_WIDTH - 1 : 0] Fre_word = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
Fre_word <= 0;
end
Expand All @@ -63,12 +63,12 @@ always @(posedge clk_in) begin
end

reg [PHASE_WIDTH - 1 : 0] addr_r0 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
addr_r0 <= addr_r0 + Fre_word;
end

reg [9:0] addr_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
addr_r1 <= addr_r0[PHASE_WIDTH - 1 : PHASE_WIDTH - 10];
end

Expand Down Expand Up @@ -356,7 +356,7 @@ always @(*) begin
end

reg signed [OUTPUT_WIDTH - 1 : 0] FM_out_r1 = 0;
always @(posedge clk_in) begin
always @(posedge clk) begin
if (RST) begin
FM_out_r1 <= 0;
end
Expand Down
0 ...ply/DSP/Advance/FFT/Flow_FFT_IFFT/BF_op.v → ...ply/DSP/Advance/FFT/Flow_FFT_IFFT/BF_op.v
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0 ...DSP/Advance/FFT/Flow_FFT_IFFT/cmpl_mult.v → ...DSP/Advance/FFT/Flow_FFT_IFFT/cmpl_mult.v
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0 ...Apply/DSP/Advance/FFT/Flow_FFT_IFFT/fft.v → ...Apply/DSP/Advance/FFT/Flow_FFT_IFFT/fft.v
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0 ...DSP/Advance/FFT/Flow_FFT_IFFT/fft_stage.v → ...DSP/Advance/FFT/Flow_FFT_IFFT/fft_stage.v
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0 ...pply/DSP/Advance/Filter/CIC/CIC_DOWN_S2.v → ...pply/DSP/Advance/Filter/CIC/CIC_DOWN_S2.v
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