Release Notes

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Release Notes

v1.0.0

• Initial release of P4->NetFPGA repository.
• Built on:
  • Xilinx Vivado v2016.4
  • Xilinx P4-SDNet v2017.1.1
• Projects:
  • switch_calc
  • tcp_monitor
  • In-band Network Telemetry
  • Ethernet Learning Switch

v1.1.0

• This commit is compatible with SDNet v2017.1.1 and Vivado 2016.4

v1.2.0

• This commit is compatible with SDNet 2017.4 and Vivado 2016.4

v1.2.1

• This is the latest commit that supports SDNet 2017.4 and Vivado 2016.4
• A few minor bug fixes over v1.2.0

v1.3.0

• This is the first release that is compatible with SDNet 2018.1 and Vivado 2016.4

• IP and MAC addresses can be passed into CLI commands

• Using input arbiter that implements DRR rather than original input arbiter

• Updated reg_rw, reg_raw, reg_praw to be more scalable (2 cycles for BRAM read)

• Updated SimpleSumeSwitch Architecture definition:

  1. digest_data must be 256 bits rather than 80 bits now
  2. If the P4 program sends a packet over DMA to the CPU, the digest_data will be prepended to the pkt.
  3. The drop field is redundant and hence no longer does anything if set. If the P4 program want to drop a packet, set the dst_port field to 0. The drop field will be removed.
  4. The verilog wrapper module around the SDNet generated module no longer performs byte endianess swapping to keep it is as simple as possible. This means that scapy fields for digest_data fields should be little endian rather than big endian now. Also make sure to list the digest_data fields in the correct order in both the P4 program and the sss_sdnet_tuples.py file.
  5. Had to increase the width of the TUSER bus connecting the nf_sume_sdnet module and the sss_output_queues module in order to accomodate for the larger digest_data.

• Users will need to either: (1) $ cd $SUME_FOLDER/lib/hw/contrib/cores/sss_output_queues_v2_0_0/ && make or (2) $ cd $SUME_FOLDER && make in order for things to work properly.

v1.3.1

• Updated the SimpleSumeSwitch architecture to only prepend the digest_data to the packet upon forwarding to SW if the send_dig_to_cpu bit is set.