I see something like the following error when I try to start the CLI tool:
root@nf-server06:CLI$ ./P4_SWITCH_CLI.py
WARNING: No route found for IPv6 destination :: (no default route?)
loading libsume..
loading libsume..
loading libcam..
Traceback (most recent call last):
File "./P4_SWITCH_CLI.py", line 36, in <module>
import p4_regs_api, p4_tables_api
File "/root/si317/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/sw/CLI/p4_tables_api.py", line 60, in <module>
libcam=cdll.LoadLibrary(os.path.expandvars('$P4_PROJECT_DIR/sw/CLI/libcam.so'))
File "/usr/lib/python2.7/ctypes/__init__.py", line 443, in LoadLibrary
return self._dlltype(name)
File "/usr/lib/python2.7/ctypes/__init__.py", line 365, in __init__
self._handle = _dlopen(self._name, mode)
OSError: libsumereg.so: cannot open shared object file: No such file or directory
A: The issue here is that your LD_LIBRARY_PATH environment variable does not include the $SUME_SDNET/sw/sume directory. First run $ export LD_LIBRARY_PATH=${SUME_SDNET}/sw/sume:${LD_LIBRARY_PATH} then try to start the CLI tool again.
How can I check if my design meets the timing requirements?
A: This is one of those details in FPGA design that is largely quoted as one of the most difficult problems to solve. There are lots of great online references that explain what it means to make a design "meet timing". Here is a great place to start. You can check if your design meets timing after you have run "place and route" or implementation. Generating the bitstream consists of running synthesis then implementation then bitstream generation. So after you've run $ make in $NF_DESIGN_DIR open up the Vivado project and check if there are any "Failed Routes":
$ vivado $NF_DESIGN_DIR/hw/project/simple_sume_switch.xpr
The "Failed Routes" will be indicated in the "Design Runs" window as indicated at the bottom right of the screen shot below.
