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Update register map for hw and sw test & submodule version #10

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Update register map for hw and sw test & submodule version #10

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e982626
Update
zhukun-wang Mar 16, 2024
a5e30b3
Update Submodule
zhukun-wang Mar 18, 2024
aeece81
Merge branch 'NetFPGA:main' into update
zhukun-wang Jun 7, 2024
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12 changes: 6 additions & 6 deletions hw/projects/reference_nic/hw/tcl/reference_nic_defines.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -32,18 +32,18 @@
# Segments Assignment #
#######################
#M00
set M00_BASEADDR 0x00010000
set M00_HIGHADDR 0x00010FFF
set M00_BASEADDR 0x00200000
set M00_HIGHADDR 0x00200FFF
set M00_SIZEADDR 0x1000

#M01
set M01_BASEADDR 0x00020000
set M01_HIGHADDR 0x00020FFF
set M01_BASEADDR 0x00210000
set M01_HIGHADDR 0x00210FFF
set M01_SIZEADDR 0x1000

#M02
set M02_BASEADDR 0x00030000
set M02_HIGHADDR 0x00030FFF
set M02_BASEADDR 0x00220000
set M02_HIGHADDR 0x00220FFF
set M02_SIZEADDR 0x1000

##M03
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6 changes: 3 additions & 3 deletions hw/projects/reference_nic/hw/tcl/reference_nic_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -212,9 +212,9 @@ CONFIG.S00_SINGLE_THREAD {1} \
CONFIG.M00_A00_ADDR_WIDTH {16} \
CONFIG.M01_A00_ADDR_WIDTH {16} \
CONFIG.M02_A00_ADDR_WIDTH {16} \
CONFIG.M00_A00_BASE_ADDR {0x0000000000010000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000020000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000030000}] [get_ips axi_crossbar_0]
CONFIG.M00_A00_BASE_ADDR {0x0000000000200000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000210000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000220000}] [get_ips axi_crossbar_0]
set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci]
reset_target all [get_ips axi_crossbar_0]
generate_target all [get_ips axi_crossbar_0]
Expand Down
12 changes: 6 additions & 6 deletions hw/projects/reference_router/hw/tcl/reference_router_defines.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -34,18 +34,18 @@
# Segments Assignment #
#######################
#M00
set M00_BASEADDR 0x00010000
set M00_HIGHADDR 0x00010FFF
set M00_BASEADDR 0x00200000
set M00_HIGHADDR 0x00200FFF
set M00_SIZEADDR 0x1000

#M01
set M01_BASEADDR 0x00020000
set M01_HIGHADDR 0x00020FFF
set M01_BASEADDR 0x00210000
set M01_HIGHADDR 0x00210FFF
set M01_SIZEADDR 0x1000

#M02
set M02_BASEADDR 0x00030000
set M02_HIGHADDR 0x00030FFF
set M02_BASEADDR 0x00220000
set M02_HIGHADDR 0x00220FFF
set M02_SIZEADDR 0x1000

##M03
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6 changes: 3 additions & 3 deletions hw/projects/reference_router/hw/tcl/reference_router_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -219,9 +219,9 @@ CONFIG.S00_SINGLE_THREAD {1} \
CONFIG.M00_A00_ADDR_WIDTH {16} \
CONFIG.M01_A00_ADDR_WIDTH {16} \
CONFIG.M02_A00_ADDR_WIDTH {16} \
CONFIG.M00_A00_BASE_ADDR {0x0000000000010000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000020000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000030000}] [get_ips axi_crossbar_0]
CONFIG.M00_A00_BASE_ADDR {0x0000000000200000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000210000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000220000}] [get_ips axi_crossbar_0]
set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci]
reset_target all [get_ips axi_crossbar_0]
generate_target all [get_ips axi_crossbar_0]
Expand Down
12 changes: 6 additions & 6 deletions hw/projects/reference_switch/hw/tcl/reference_switch_defines.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -33,18 +33,18 @@
# Segments Assignment #
#######################
#M00
set M00_BASEADDR 0x00010000
set M00_HIGHADDR 0x00010FFF
set M00_BASEADDR 0x00200000
set M00_HIGHADDR 0x00200FFF
set M00_SIZEADDR 0x1000

#M01
set M01_BASEADDR 0x00020000
set M01_HIGHADDR 0x00020FFF
set M01_BASEADDR 0x00210000
set M01_HIGHADDR 0x00210FFF
set M01_SIZEADDR 0x1000

#M02
set M02_BASEADDR 0x00030000
set M02_HIGHADDR 0x00030FFF
set M02_BASEADDR 0x00220000
set M02_HIGHADDR 0x00220FFF
set M02_SIZEADDR 0x1000

##M03
Expand Down
6 changes: 3 additions & 3 deletions hw/projects/reference_switch/hw/tcl/reference_switch_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -215,9 +215,9 @@ CONFIG.S00_SINGLE_THREAD {1} \
CONFIG.M00_A00_ADDR_WIDTH {16} \
CONFIG.M01_A00_ADDR_WIDTH {16} \
CONFIG.M02_A00_ADDR_WIDTH {16} \
CONFIG.M00_A00_BASE_ADDR {0x0000000000010000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000020000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000030000}] [get_ips axi_crossbar_0]
CONFIG.M00_A00_BASE_ADDR {0x0000000000200000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000210000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000220000}] [get_ips axi_crossbar_0]
set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci]
reset_target all [get_ips axi_crossbar_0]
generate_target all [get_ips axi_crossbar_0]
Expand Down
12 changes: 6 additions & 6 deletions hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite_defines.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -32,18 +32,18 @@
# Segments Assignment #
#######################
#M00
set M00_BASEADDR 0x00010000
set M00_HIGHADDR 0x00010FFF
set M00_BASEADDR 0x00200000
set M00_HIGHADDR 0x00200FFF
set M00_SIZEADDR 0x1000

#M01
set M01_BASEADDR 0x00020000
set M01_HIGHADDR 0x00020FFF
set M01_BASEADDR 0x00210000
set M01_HIGHADDR 0x00210FFF
set M01_SIZEADDR 0x1000

#M02
set M02_BASEADDR 0x00030000
set M02_HIGHADDR 0x00030FFF
set M02_BASEADDR 0x00220000
set M02_HIGHADDR 0x00220FFF
set M02_SIZEADDR 0x1000

##M03
Expand Down
6 changes: 3 additions & 3 deletions hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -216,9 +216,9 @@ CONFIG.S00_SINGLE_THREAD {1} \
CONFIG.M00_A00_ADDR_WIDTH {16} \
CONFIG.M01_A00_ADDR_WIDTH {16} \
CONFIG.M02_A00_ADDR_WIDTH {16} \
CONFIG.M00_A00_BASE_ADDR {0x0000000000010000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000020000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000030000}] [get_ips axi_crossbar_0]
CONFIG.M00_A00_BASE_ADDR {0x0000000000200000}\
CONFIG.M01_A00_BASE_ADDR {0x0000000000210000}\
CONFIG.M02_A00_BASE_ADDR {0x0000000000220000}] [get_ips axi_crossbar_0]
set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci]
reset_target all [get_ips axi_crossbar_0]
generate_target all [get_ips axi_crossbar_0]
Expand Down