resolve fastsim-2 merge conflicts

NREL · Oct 18, 2023 · b25e09d · b25e09d
2 parents fd113fa + 0559171
commit b25e09d
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/rust/fastsim-core/src/imports.rs b/rust/fastsim-core/src/imports.rs
@@ -1,4 +1,4 @@
-pub(crate) use anyhow;
+pub(crate) use anyhow::{self, Context};
 pub(crate) use bincode;
 pub(crate) use log;
 pub(crate) use ndarray::{array, concatenate, s, Array, Array1, Axis};

diff --git a/rust/fastsim-core/src/simdrive/simdrive_iter.rs b/rust/fastsim-core/src/simdrive/simdrive_iter.rs
@@ -49,12 +49,12 @@ impl SimDriveVec {
         if parallelize {
             self.0.par_iter_mut().enumerate().try_for_each(|(i, sd)| {
                 sd.sim_drive(None, None)
-                    .map_err(|err| err.context(format!("simdrive idx:{}", i)))
+                    .with_context(|| format!("simdrive idx: {}", i))
             })?;
         } else {
             self.0.iter_mut().enumerate().try_for_each(|(i, sd)| {
                 sd.sim_drive(None, None)
-                    .map_err(|err| err.context(format!("simdrive idx:{}", i)))
+                    .with_context(|| format!("simdrive idx: {}", i))
             })?;
         }
         Ok(())