Modify the format

README.md

@@ -1,2 +1,3 @@
 # PipelineCPU
-A pipelined CPU implemented by Verilog
+A pipelined CPU implemented by Verilog.
+

alu.v

@@ -1,40 +1,40 @@
 `include "ctrl_encode_def.v"
 
-module alu(A, B, ALUOp, C, Zero,PC);
-   input  signed [31:0] A, B;
-   input         [4:0]  ALUOp;
+module alu(A, B, ALUOp, C, Zero, PC);
+   input signed [31:0] A, B;
+   input [4:0] ALUOp;
    input [31:0] PC;
    output signed [31:0] C;
    output Zero;
 
    reg [31:0] C;
-   integer    i;
+   integer i;
 
-   always @( * ) begin
-      case ( ALUOp )
-         `ALUOp_nop  :C=A;
-         `ALUOp_lui  :C=B;
-         `ALUOp_auipc:C=PC+B;
+   always @(*) begin
+      case (ALUOp)
+         `ALUOp_nop  : C = A;
+         `ALUOp_lui  : C = B;
+         `ALUOp_auipc: C = PC + B;
 
-         `ALUOp_add:C=A+B;
-         `ALUOp_sub:C=A-B;
-         `ALUOp_xor:C=A^B;
-         `ALUOp_or :C=A|B;
-         `ALUOp_and:C=A&B;
-         `ALUOp_sll:C=A<<B;
-         `ALUOp_srl:C=A>>B;
-         `ALUOp_sra:C=A>>>B;
+         `ALUOp_add: C = A + B;
+         `ALUOp_sub: C = A - B;
+         `ALUOp_xor: C = A ^ B;
+         `ALUOp_or : C = A | B;
+         `ALUOp_and: C = A & B;
+         `ALUOp_sll: C = A << B;
+         `ALUOp_srl: C = A >> B;
+         `ALUOp_sra: C = A >>> B;
 
-         `ALUOp_bne :C={31'b0,(A==B)};
-         `ALUOp_blt :C={31'b0,(A>=B)};
-         `ALUOp_bge :C={31'b0,(A<B)};
-         `ALUOp_bltu:C={31'b0,($unsigned(A)>=$unsigned(B))};
-         `ALUOp_bgeu:C={31'b0,($unsigned(A)<$unsigned(B))};
-         `ALUOp_slt :C={31'b0,(A<B)};
-         `ALUOp_sltu:C={31'b0,($unsigned(A)<$unsigned(B))};
+         `ALUOp_bne : C = {31'b0, (A == B)};
+         `ALUOp_blt : C = {31'b0, (A >= B)};
+         `ALUOp_bge : C = {31'b0, (A < B)};
+         `ALUOp_bltu: C = {31'b0, ($unsigned(A) >= $unsigned(B))};
+         `ALUOp_bgeu: C = {31'b0, ($unsigned(A) < $unsigned(B))};
+         `ALUOp_slt : C = {31'b0, (A < B)};
+         `ALUOp_sltu: C = {31'b0, ($unsigned(A) < $unsigned(B))};
       endcase
    end
 
-   assign Zero = (C == 32'b0);            // 运算结果是否为零，若为零则表示满足有条件跳转的条件
+   assign Zero = (C == 32'b0); // Jump condition
 
 endmodule

ctrl.v

@@ -1,53 +1,31 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 2023/06/25 15:02:32
-// Design Name: 
-// Module Name: ctrl
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module ctrl(Op, Funct7, Funct3,
-            RegWrite, MemWrite,
-            EXTOp, ALUOp, NPCOp, 
-            ALUSrc, GPRSel, WDSel, dm_ctrl,
-            use_rs1, use_rs2
-            );
+module ctrl(
+  Op, Funct7, Funct3, 
+  RegWrite, MemWrite, EXTOp, ALUOp, NPCOp, 
+  ALUSrc, GPRSel, WDSel, dm_ctrl,
+  use_rs1, use_rs2
+);
 
-    input  [6:0] Op;       // opcode
-    input  [6:0] Funct7;    // funct7
-    input  [2:0] Funct3;    // funct3
+    input [6:0] Op; // Opcode
+    input [6:0] Funct7; // Funct7
+    input [2:0] Funct3; // Funct3
 
-    output       RegWrite; // control signal for register write
-    output       MemWrite; // control signal for memory write
-    output [5:0] EXTOp;    // control signal to signed extension
-    output [4:0] ALUOp;    // ALU opertion
-    output [2:0] NPCOp;    // next pc operation
-    output       ALUSrc;   // ALU source for A
+    output RegWrite; // Control signal for register write
+    output MemWrite; // Control signal for memory write
+    output [5:0] EXTOp; // Control signal to signed extension
+    output [4:0] ALUOp; // ALU opertion
+    output [2:0] NPCOp; // Next PC operation
+    output ALUSrc; // ALU source for A
     output [2:0] dm_ctrl;
-    output [1:0] GPRSel;   // general purpose register selection
-    output [1:0] WDSel;    // (register) write data selection
-    output  use_rs1, use_rs2;
+    output [1:0] GPRSel; // General purpose register selection
+    output [1:0] WDSel; // Write data selection
+    output use_rs1, use_rs2;
 
   // r format
-    wire rtype  = ~Op[6]&Op[5]&Op[4]&~Op[3]&~Op[2]&Op[1]&Op[0]; //0110011
-    wire i_add  = rtype& ~Funct7[6]&~Funct7[5]&~Funct7[4]&~Funct7[3]&~Funct7[2]&~Funct7[1]&~Funct7[0]&~Funct3[2]&~Funct3[1]&~Funct3[0]; // add 0000000 000
-    wire i_sub  = rtype& ~Funct7[6]& Funct7[5]&~Funct7[4]&~Funct7[3]&~Funct7[2]&~Funct7[1]&~Funct7[0]&~Funct3[2]&~Funct3[1]&~Funct3[0]; // sub 0100000 000
-    wire i_or   = rtype& ~Funct7[6]&~Funct7[5]&~Funct7[4]&~Funct7[3]&~Funct7[2]&~Funct7[1]&~Funct7[0]& Funct3[2]& Funct3[1]&~Funct3[0]; // or 0000000 110
-    wire i_and  = rtype& ~Funct7[6]&~Funct7[5]&~Funct7[4]&~Funct7[3]&~Funct7[2]&~Funct7[1]&~Funct7[0]& Funct3[2]& Funct3[1]& Funct3[0]; // and 0000000 111
+    wire rtype  = ~Op[6] & Op[5] & Op[4] & ~Op[3] & ~Op[2] & Op[1] & Op[0]; //0110011
+    wire i_add  = rtype & ~Funct7[6] &~Funct7[5] &~Funct7[4] &~Funct7[3] &~Funct7[2] &~Funct7[1] &~Funct7[0] &~Funct3[2]&~Funct3[1]&~Funct3[0]; // add 0000000 000
+    wire i_sub  = rtype & ~Funct7[6] & Funct7[5] &~Funct7[4] &~Funct7[3] &~Funct7[2] &~Funct7[1] &~Funct7[0] &~Funct3[2]&~Funct3[1]&~Funct3[0]; // sub 0100000 000
+    wire i_or   = rtype & ~Funct7[6] &~Funct7[5] &~Funct7[4] &~Funct7[3] &~Funct7[2] &~Funct7[1] &~Funct7[0] & Funct3[2]& Funct3[1]&~Funct3[0]; // or 0000000 110
+    wire i_and  = rtype & ~Funct7[6] &~Funct7[5] &~Funct7[4] &~Funct7[3] &~Funct7[2] &~Funct7[1] &~Funct7[0] & Funct3[2]& Funct3[1]& Funct3[0]; // and 0000000 111
     wire i_xor  = rtype & ~Funct7[6] & ~Funct7[5] & ~Funct7[4] & ~Funct7[3] & ~Funct7[2] & ~Funct7[1] & ~Funct7[0] & Funct3[2] & ~Funct3[1] & ~Funct3[0]; // xor 0000000 100
     wire i_sll  = rtype & ~Funct7[6] & ~Funct7[5] & ~Funct7[4] & ~Funct7[3] & ~Funct7[2] & ~Funct7[1] & ~Funct7[0] & ~Funct3[2] & ~Funct3[1] & Funct3[0]; // sll 0000000 001
     wire i_slt  = rtype & ~Funct7[6] & ~Funct7[5] & ~Funct7[4] & ~Funct7[3] & ~Funct7[2] & ~Funct7[1] & ~Funct7[0] & ~Funct3[2] & Funct3[1] & ~Funct3[0]; // slt 0000000 010

ctrl_encode_def.v

@@ -1,38 +1,14 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 2023/06/25 14:45:07
-// Design Name: 
-// Module Name: ctrl_encode_def
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-// NPC control signal
 `define NPC_PLUS4   3'b000
 `define NPC_BRANCH  3'b001
 `define NPC_JUMP    3'b010
 `define NPC_JALR 3'b100
 
-// ALU control signal
 `define ALU_NOP   3'b000 
 `define ALU_ADD   3'b001
 `define ALU_SUB   3'b010 
 `define ALU_AND   3'b011
 `define ALU_OR    3'b100
 
-//EXT CTRL itype, stype, btype, utype, jtype
 `define EXT_CTRL_ITYPE_SHAMT 6'b100000
 `define EXT_CTRL_ITYPE	6'b010000
 `define EXT_CTRL_STYPE	6'b001000

sccomp_tb.v

@@ -16,7 +16,7 @@ module sccomp_tb();
       $dumpfile("wave.vcd");
       $dumpvars(0, xgriscv.U_SCPU);
 
-      $readmemh( "T.dat" , xgriscv.U_imem.RAM); // load instructions into instruction memory
+      $readmemh( "Test_37_Instr.dat" , xgriscv.U_imem.RAM); // load instructions into instruction memory
       clk = 1;
       rstn = 1;
       #5 ;