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Linux Porting Guide
Marvell provides the Linux Support Package (LSP) as a patch on top of the Vanilla Kernel version 3.10 or later, which can be downloaded from www.kernel.org. This section describes the Linux-specific changes that are required, to support a new customer board.
NOTE: The complete documentation for all drivers is available under the kernel’s Documentation folder, for example:
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CESA: Documentation/devicetree/bindings/crypto/mvebu_cesa.txt
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USB: Documentation/devicetree/bindings/usb/usb-xhci.txt
Create a new dts file for the new board based on the matching armada-385-db.dts located at: arch/arm/boot/dts/
Update the relevant nodes in the dts file according to the board settings. Use the status variable of every node to enable or disable the unit.
For example, DT nodes for I2C#0, enabled, based on 0x11000, with clock = 100000, and I2C#1, disabled, based on 0x11100, with clock = 100KHz.
Enable i2c #0:
i2c0: i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
Disable i2c #1:
i2c1: i2c@11100 {
status = "disabled";
clock-frequency = <100000>;
};
Complete information is available in the folder: Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt.
NOTE: It is important to remove the irrelevant nodes after updating the relevant nodes.
There are two ways to connect the VBUS control: via CPU GPIO or IO Expander. The following are the device tree configurations for each mode:
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Expander mode connected via MPP2/3 connected to NXP IO Expander (pca953X):
i2c0: i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
expander1: pca9555@21
{
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
pinctrl {
i2c0_pins: i2c-pins-0
{
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c0";
};
};
usb3_phy_exp1: usb3-phy-exp1
{
status = "disabled";
compatible = "usb-nop-xceiv";
vcc-supply = <®_usb3_vbus_exp1>;
};
reg_usb3_vbus_exp1: usb3-vbus-exp1
{
status = "disabled";
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
};
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IO Expander mode connected via CPU MPP44:
pinctrl {
xhci0_vbus_pins: xhci0-vbus-pins
{
marvell,pins = "mpp44";
marvell,function = "gpio";
};
};
/* usb3 vbus controlled via gpio pin */
usb3_phy_gpio: usb3-phy-gpio
{
status = "disabled";
compatible = "usb-nop-xceiv";
vcc-supply = <®_usb3_vbus_gpio>;
};
reg_usb3_vbus_gpio: usb3-vbus-gpio
{
status = "disabled";
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
The following is an example for enabling serial port #0, with 200MHz clock reference. To enable serial port #1, enable the node named serial@12100.
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
Complete information is available in the folder: Documentation/devicetree/bindings.
To configure the device tree for the SOHO switch, do the following:
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Disable the ETH ports PHY register (set eth ports’ phyreg to 999, which means there is no PHY connected in the corresponding ETH port).
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Update the switch node in the DT according to the following node properties:
Device Tree Configuration
| Field | Description |
|---|---|
compatible |
Set to "marvell,mv_switch" |
status |
Set to "disabled" or "okay" |
index |
Switch index, generally this is zero since systems usually only have a single switch |
phy_addr |
SMI PHY address to access switch |
gbe_port |
SoC GBE port to which switch uplink port is connected |
cpuPort |
Switch port to which SoC CPU is connected |
vid |
Switch default DB number |
port_mask |
Switch port mask, if bitn is 1, then the n switch port is valid in physical |
connected_port_mask |
Switch ports that are being used |
forced_link_port_mask |
Switch ports that are forced link up |
mtu |
Switch MTU |
smi_scan_mode |
Switch SMI scan mode, encoded as follows: * 0 = SMI auto scan mode, scan 0 or 0x10 base address to find the Quarter Deck (QD) * 1 = SMI manual mode, use QD located at manually-defined base address * 2 = SMI multi-address mode, use QD at base address and use indirect access |
qsgmii_module |
Is a QSGMII module on the switch, 0 is no, 1 is yes |
gephy_on_port |
Switch GE PHY ports bitmask |
rgmiia_on_port |
Switch RGMII ports bitmask, generally these ports are uplink ports |
switch_irq |
If the switch uses IRQ mode to report events, then switch_irq is valid and it is the switch IRQ number in the system; if PHY polling unit is enabled and IRQ is disabled, the switch_irq should be 0xffffffff(-1) |
is_speed_2000 |
If the value is not zero, then the switch CPU port works in 2 Gbps mode |
rgmii_rx_timing_delay |
RGMII receive timing control: * 0 = default, there is no delay * 1 = add delay to RXCLK for IND inputs when port is in RGMII mode |
rgmii_tx_timing_delay |
RGMII transmit timing control: * 0 = default, there is no delay * 1 = add delay to GTXCLK for OUTD outputs when port is in RGMII mode |
The following example enables the switch with the default settings:
switch {
status = "okay";
}
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii";
};
ethernet@30000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii";
};
mdio {
phy0: ethernet-phy@0
{
reg = <999>;
};
phy1: ethernet-phy@1
{
reg = <999>;
};
};
The following is sample code that configures an Ethernet port with SGMII and with no PHY connected to the MAC. Each Ethernet unit is configured by an Ethernet node and corresponding PHY node, as shown below:
ethernet@30000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
phy1: ethernet-phy@1 {
reg = <999>;
};
ethernet node:
Tables below describe the Ethernet variables:
Ethernet Variables:
| Property | Description | Possible Values |
|---|---|---|
status |
Port status |
“okay” or “disabled” |
phy |
The phandle for the PHY connected to this Ethernet controller |
|
phy-mode |
Mode of the PHY connected to the Ethernet controller |
“sgmii” or “rgmii” |
PHY Variables:
| Property | Description | Possible Values |
|---|---|---|
reg |
The ID number for the PHY |
Usually small integer number, and 999 if no PHY is connected to the Ethernet port |
The complete information is available in the following folders:
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Ethernet: Documentation/devicetree/bindings/marvell.txt
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PHY: Documentation/devicetree/bindings/net/phy.txt
The following is an example of enabling the NAND Flash: NAND Flash Settings:
nfc: nand@d0000 {
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = <200000000>;
nfc,nfc-mode = "normal"; /* normal or ganged */
nfc,nfc-dma = <0>; /* 0 for no, 1 for dma */
nfc,nfc-width = <8>;
nfc,ecc-type = <1>; /* 4 bit */
nfc,num-cs = <1>;
mtd0@00000000 {
label = "U-Boot";
reg = <0x00000000 0x00600000>;
read-only;
};
mtd1@00080000 {
label = "uImage";
reg = <0x00600000 0x00400000>;
read-only;
};
mtd2@00140000 {
label = "Root";
reg = <0x00a00000 0x3f600000>;
};
};
Verify that the NAND device ID is defined in the nand_ids.c file that is located in the drivers/mtd/nand/ directory (refer to the U-Boot Porting Guide, paragraph "Adding Support for a New NAND Device"). Complete information is available in the folder: Documentation/devicetree/bindings/mtd/mvebu_nfc.txt.