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add simulator Cache as class SimCache/SimLRUCache(with test)
Summary: add class SimCache(base class with instrumentation api) and SimLRUCache(derived class with detailed implementation) which is used as an instrumented block cache that can predict hit rate for different cache size Test Plan: Add a test case in `db_block_cache_test.cc` called `SimCacheTest` to test basic logic of SimCache. Also add option `-simcache_size` in db_bench. if set with a value other than -1, then the benchmark will use this value as the size of the simulator cache and finally output the simulation result. ``` [[email protected] ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 1000000 RocksDB: version 4.8 Date: Tue May 17 16:56:16 2016 CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz CPUCache: 20480 KB Keys: 16 bytes each Values: 100 bytes each (50 bytes after compression) Entries: 1000000 Prefix: 0 bytes Keys per prefix: 0 RawSize: 110.6 MB (estimated) FileSize: 62.9 MB (estimated) Write rate: 0 bytes/second Compression: Snappy Memtablerep: skip_list Perf Level: 0 WARNING: Assertions are enabled; benchmarks unnecessarily slow ------------------------------------------------ DB path: [/tmp/rocksdbtest-112628/dbbench] fillseq : 6.809 micros/op 146874 ops/sec; 16.2 MB/s DB path: [/tmp/rocksdbtest-112628/dbbench] readrandom : 6.343 micros/op 157665 ops/sec; 17.4 MB/s (1000000 of 1000000 found) SIMULATOR CACHE STATISTICS: SimCache LOOKUPs: 986559 SimCache HITs: 264760 SimCache HITRATE: 26.84% [[email protected] ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 10000000 RocksDB: version 4.8 Date: Tue May 17 16:57:10 2016 CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz CPUCache: 20480 KB Keys: 16 bytes each Values: 100 bytes each (50 bytes after compression) Entries: 1000000 Prefix: 0 bytes Keys per prefix: 0 RawSize: 110.6 MB (estimated) FileSize: 62.9 MB (estimated) Write rate: 0 bytes/second Compression: Snappy Memtablerep: skip_list Perf Level: 0 WARNING: Assertions are enabled; benchmarks unnecessarily slow ------------------------------------------------ DB path: [/tmp/rocksdbtest-112628/dbbench] fillseq : 5.066 micros/op 197394 ops/sec; 21.8 MB/s DB path: [/tmp/rocksdbtest-112628/dbbench] readrandom : 6.457 micros/op 154870 ops/sec; 17.1 MB/s (1000000 of 1000000 found) SIMULATOR CACHE STATISTICS: SimCache LOOKUPs: 1059764 SimCache HITs: 374501 SimCache HITRATE: 35.34% [[email protected] ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 100000000 RocksDB: version 4.8 Date: Tue May 17 16:57:32 2016 CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz CPUCache: 20480 KB Keys: 16 bytes each Values: 100 bytes each (50 bytes after compression) Entries: 1000000 Prefix: 0 bytes Keys per prefix: 0 RawSize: 110.6 MB (estimated) FileSize: 62.9 MB (estimated) Write rate: 0 bytes/second Compression: Snappy Memtablerep: skip_list Perf Level: 0 WARNING: Assertions are enabled; benchmarks unnecessarily slow ------------------------------------------------ DB path: [/tmp/rocksdbtest-112628/dbbench] fillseq : 5.632 micros/op 177572 ops/sec; 19.6 MB/s DB path: [/tmp/rocksdbtest-112628/dbbench] readrandom : 6.892 micros/op 145094 ops/sec; 16.1 MB/s (1000000 of 1000000 found) SIMULATOR CACHE STATISTICS: SimCache LOOKUPs: 1150767 SimCache HITs: 1034535 SimCache HITRATE: 89.90% ``` Reviewers: IslamAbdelRahman, andrewkr, sdong Reviewed By: sdong Subscribers: MarkCallaghan, andrewkr, dhruba, leveldb Differential Revision: https://reviews.facebook.net/D57999
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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved. | ||
// This source code is licensed under the BSD-style license found in the | ||
// LICENSE file in the root directory of this source tree. An additional grant | ||
// of patent rights can be found in the PATENTS file in the same directory. | ||
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#pragma once | ||
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#include <stdint.h> | ||
#include <memory> | ||
#include <string> | ||
#include "rocksdb/cache.h" | ||
#include "rocksdb/slice.h" | ||
#include "rocksdb/status.h" | ||
#include "util/lru_cache_handle.h" | ||
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namespace rocksdb { | ||
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class SimCache; | ||
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// For instrumentation purpose, use NewSimCache instead of NewLRUCache API | ||
// NewSimCache is a wrapper function returning a SimCache instance that can | ||
// have additional interface provided in Simcache class besides Cache interface | ||
// to predict block cache hit rate without actually allocating the memory. It | ||
// can help users tune their current block cache size, and determine how | ||
// efficient they are using the memory. | ||
extern std::shared_ptr<SimCache> NewSimCache(std::shared_ptr<Cache> cache, | ||
size_t sim_capacity, | ||
int num_shard_bits); | ||
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class SimCache : public Cache { | ||
public: | ||
SimCache() {} | ||
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virtual ~SimCache() {} | ||
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// returns the maximum configured capacity of the simcache for simulation | ||
virtual size_t GetSimCapacity() const = 0; | ||
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// simcache doesn't provide internal handler reference to user, so always | ||
// PinnedUsage = 0 and the behavior will be not exactly consistent the | ||
// with real cache. | ||
// returns the memory size for the entries residing in the simcache. | ||
virtual size_t GetSimUsage() const = 0; | ||
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// sets the maximum configured capacity of the simcache. When the new | ||
// capacity is less than the old capacity and the existing usage is | ||
// greater than new capacity, the implementation will purge old entries | ||
// to fit new capapicty. | ||
virtual void SetSimCapacity(size_t capacity) = 0; | ||
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// returns the lookup times of simcache | ||
virtual uint64_t get_lookup_counter() const = 0; | ||
// returns the hit times of simcache | ||
virtual uint64_t get_hit_counter() const = 0; | ||
// returns the hit rate of simcache | ||
virtual double get_hit_rate() const = 0; | ||
// reset the lookup and hit counters | ||
virtual void reset_counter() = 0; | ||
// String representation of the statistics of the simcache | ||
virtual std::string ToString() const = 0; | ||
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private: | ||
SimCache(const SimCache&); | ||
SimCache& operator=(const SimCache&); | ||
}; | ||
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} // namespace rocksdb |
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